MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 961

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

TER 7-22
TFCR 7-125, 7-272, 7-321
TGATE 7-19
TGCR 7-20
Thermal Characteristics 10-2
Timeout 7-308
Timer Block Diagram 7-17
Timer Examples 7-23
Timers 7-17, 9-25
Time-Slot 1-15, 14
TIN 7-18
TM_BASE 7-13
TMR 7-21
TMS 2-12
TODR 7-121, 7-175, 7-200
Totally Transparent 7-220
TOUT 7-18
TP Bit 5-49
TR Bit 5-49, 5-51, 5-52, 5-53
Trace 5-37, 5-39
Trace Exception 5-39, 5-42, 5-45, 5-46, 5-
Trace Mode 5-7
Trace on Instruction Execution 5-59
Transfer Format 7-319
Transition to BDM 5-62
Transmission Line Configuration 7-194
TRANSMIT ABORT REQUEST Command
Transmit on Demand 7-121
Transmit/Receive Process 7-315
Transmitter 7-275
Transmitter Shortcut 7-275
Transmitting and Receiving 7-208
Transparent 7-115, 7-116, A-1
Cascaded Mode 7-19
Deriving SWT Timeout 6-36
General-Purpose Timer 7-17
RISC Timer Tables 7-11
Timer Block Diagram 7-17
Timer Examples 7-23
TM_BASE 7-13
Wake-Up Timer 7-151
4-Bit SYNC 7-223
Achieving Synchronization in
External Synchronization Signals 7-223
49, 5-51, 5-56
7-307
Transparent Mode 7-223
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68356 USER’S MANUAL
Go to: www.freescale.com
Transparent Channel Frame Reception
Transparent Channel Frame Transmission
Transparent Command Set 7-226, 7-297
Transparent Controller 7-220, 7-291
Transparent CRC 7-112
Transparent Error-Handling Procedure 7-
Transparent Memory Map 7-225
Transparent Mode Register 7-228
Transparent NMSI Example 7-303
Transparent Protocol 7-268
Transparent Receive Buffer Descriptor 7-
Transparent Reception Processing 7-293
Transparent Transmit Buffer Descriptor 7-
Transparent TSA Example 7-304
TRAP instruction 5-39
TRIS 2-12, 6-26
TRLXQ 6-74
TRR 7-22
TRST 2-12
TS 6-26, 6-60, 6-63, 6-68, 9-32
TSA 7-170
TSA Transmission Line Configuration 7-195
TXD 7-101, 7-358
In-Line Synchronization Pattern 7-223
PIP 7-338
Promiscuous 7-220
SCC Transparent Example 7-233
Sending Transparent Frames Between
SMC 7-291
Totally Transparent 7-220
Transparent Channel Frame Reception
Transparent Channel Frame
Transparent Command Set 7-226
Transparent Controller 7-220
Transparent Error-Handling Procedure
Transparent Receive Buffer Descriptor
Using the TSA 7-195
Processing 7-222
Processing 7-221
227, 7-298
228
230
QUICCs 7-225
Processing 7-222
Transmission Processing 7-221
7-227
7-228
Index