MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 659

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

When configured as a transmitter, the PIP generates the STB signal when data is ready in
the PIP’s output latch and the previous transfer has been acknowledged (see Figure 7-86).
The setup time and the strobe pulse width are user programmable. When configured as a
receiver, the PIP uses the STB signal to latch the input data and acknowledges the transfer
with the ACK signal. The timing of the ACK signal is user programmable.
7.13.5.1 BUSY SIGNAL. In the pulsed handshake mode, the PIP receiver can generate an
additional BUSY handshake signal, which is useful to implement the Centronics reception
interface (see Figure 7-87). The BUSY signal is an output indication of a transfer in service.
It is asserted by the Centronics receiver as soon as the data is latched into the PIP data reg-
ister. The timing of BUSY negation in relation to the ACK signal is user programmable. Two
bits in the PIP configuration register enable the assertion and negation of the BUSY signal
via the host processor software.
RISC/CPU32+
RISC/CPU32+
TX DATA
RX DATA
IN USE
IN USE
STB
ACK
Figure 7-86. Pulsed Handshake Full Cycle
WRITE FROM RISC
READ FROM RISC
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
LATCH
LATCH
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BYTE A
PIP TRANSMIT
PIP RECEIVE
BYTE A
DIR = OUTPUT
WRITE FROM HANDSHAKE
CONTROL LOGIC (DIR = OUT)
BYTE B
I/O
Parallel Interface Port (PIP)
BYTE B
PIN