MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 89

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Figure 4-8 shows the transfer of a long-word operand to an odd address in word-organized
memory, which requires three bus cycles. For the first cycle, the SIZx signals specify a long-
word transfer, and the address offset (A2–A0) is 001. Since the port width is 16 bits, only the
first byte of the long word is transferred. The slave device latches the byte and acknowl-
edges the data transfer, indicating that the port is 16 bits wide. When the processor starts
the second cycle, the SIZx signals specify that three bytes remain to be transferred with an
address offset (A2–A0) of 010. The next two bytes are transferred during this cycle. The pro-
cessor then initiates the third cycle, with the SIZx signals indicating one byte remaining to
be transferred. The address offset (A2–A0) is now 100; the port latches the final byte, and
the operation is complete. Figure 4-9 shows the associated bus transfer signal timing.
Figure 4-7. Word Operand Write Timing (8-Bit Data Port)
FC3–FC0
D31–D24
D23–D16
DSACK0
DSACK1
D15–D8
A31–A2
CLKO1
D7–D0
SIZ0
SIZ1
R/W
DS
AS
A0
A1
Freescale Semiconductor, Inc.
For More Information On This Product,
S0
MC68360 USER’S MANUAL
Go to: www.freescale.com
BYTE WRITE
S2
OP3
OP2
OP2
OP3
WORD OPERAND WRITE
S4
S0
BYTE WRITE
S2
OP3
OP3
OP3
OP3
S4
Bus Operation