MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 772

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
Applications
mode selectable for each 4K or 8K page within memory. The use of several caching modes
within the same address range is made more difficult without the MMU. The access control
unit of the MC68EC040 provides two access control registers each for data and instructions.
Each access control register allows caching modes to be defined in 16-Mbyte to 4-Gbyte
sections. This coarse division of the memory map is not ideal for all embedded applications.
The following paragraphs explain an addressing scheme that allows all parts of the memory
map to be independently available using any of the MC68EC040 caching modes on line
boundaries (a line equals 16 bytes). Since any part of the memory map is accessible as
cache-inhibited, copyback, or write-through, there is no requirement to split caching modes
on 16-Mbyte boundaries. Furthermore, since the cache mode can be selected down to the
line boundary, different areas within the same address region (e.g., DRAM) are accessible
in any or all of the three caching modes.
9.5.1 The Algorithm
Two address bits are used to divide the MC68EC040 4-Gbyte addressing range into four 1-
Gbyte sections. The only difference between the sections is the caching modes. The cach-
ing mode of one section is made cache-inhibited, serialized (address bits = 00); the next sec-
tion is made cachable, copyback (01); and the last two sections are made cachable, write-
through (1x). The address bit ordering (00, 01, 1x) allows the 1-Gbyte sections to be nested.
Address bits 00 are at the bottom of the address map, address bits 01 are in the middle, and
address bits 1x occupy the top half of the address map. Each 1-Gbyte section is mirrored
onto every other section to provide a single 1-Gbyte addressing range. The address mirror-
ing is done by externally ignoring the two address bits used to select the caching mode. The
regions are mapped into memory using the remaining 30 address bits. The caching mode
of any part of the 1-Gbyte address range is now selected by software. If the address bits
used for cache mode selection are 00, the access is cache-inhibited. If the address bits are
01, the access is a copyback. If the address bits are 10 or 11, the access is a write-through.
The address bits can be any of the top eight address bits (A31–A24) and do not need to be
contiguous.
9.5.2 Protection
This cache addressing method does not provide any internal protection from incorrectly
accessing an address with the wrong caching scheme. The answer is to rely on the software
to correctly access with the correct caching mode or to externally qualify the accesses with
the caching mode address bits. Special care is required to avoid mixing caching modes
within the same memory line. An example of the problem is a cachable and noncachable
access to the same line. A copyback access to one long word of a line will cause all four long
words of the line to be read into memory. A cache-inhibited access to another long word of
the same line would not hit in the cache, but rather hit in the external memory. A cache line
push of the copyback line can now overwrite the cache-inhibited long word in external mem-
ory. A subsequent memory access to the cache-inhibited long word of the same line will now
differ based on whether the cache push of the line has occurred. The solution is to use line
boundaries when choosing caching modes. To change the cache mode of a line from cach-
able to cache inhibited, do a CPUSH or CINVAL of the line when making the change to
ensure that the cache does not contain a copy of a cache-inhibited line. To switch from
cache inhibited to cachable, the internal caches do not require any change.
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MC68360 USER’S MANUAL
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