MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 696

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
CPM Interrupt Controller (CPIC)
7.15.2 CPM Interrupt Source Priorities
The CPIC has 28 interrupt sources that assert just one programmable interrupt request level
to the CPU32+ core. The priority between all interrupt sources is shown in Table 7-22. There
is some flexibility in the relative ordering of the interrupts in the table, but, in general, the
relative priorities are fixed in the descending order shown in the table. An interrupt from the
parallel I/O line PC0 has the highest priority, and an interrupt from the parallel I/O line PC11
has the lowest priority. A single interrupt priority number is associated with each table entry.
Note the lack of SDMA interrupt sources. The SDMA-related interrupts are reported through
each individual SCC, SMC, or SPI channel. The only true SDMA interrupt source is the
SDMA channel's bus error entry that is reported when a bus error occurs during an SDMA
access.
There are two methods to add flexibility to the table of CPM interrupt priorities: the SCC’s
relative priority option and the highest priority option.
7.15.2.1 SCC RELATIVE PRIORITY. The relative priority between the four SCCs is pro-
grammable and can be dynamically changed. In Table 7-22 there is no entry for SCC1,
SCC2, SCC3, or SCC4, but rather there are entries for SCCa, SCCb, SCCc, and SCCd
because each of the SCCs can be mapped to any of these locations. This is programmed
in the CICR and may be dynamically changed. The user can utilize this on-the-fly capability
to implement a rotating priority.
In addition, the grouping of the locations of the SCCa, SCCb, SCCc, and SCCd entries has
two options: group and spread. In the group scheme, the SCCs are all grouped together at
the top of the priority table, ahead of most of the other CPM interrupt sources. This scheme
is ideal for applications where all SCCs function at a very high data rate and interrupt latency
is very important. In the spread scheme, the SCC priorities are spread over the table so that
other sources can have lower interrupt latencies than the SCCs. This scheme is also pro-
grammed in the CICR, but it may not be dynamically modified.
7.15.2.2 HIGHEST PRIORITY INTERRUPT. In addition to the SCC relative priority option,
the user may choose one interrupt source to be of highest priority. This highest priority inter-
rupt is still within the same interrupt level as the rest of the CPIC interrupts, but is simply
serviced prior to any other interrupt in the table. If the highest priority feature is not used,
select PC0 to be the highest priority interrupt, and no modifications to the standard interrupt
priority order will occur.
This highest priority source is dynamically programmable in the CICR. This allows the user
to change a normally low priority source into a high priority source for a specified period of
time.
7-372
MC68360 USER’S MANUAL
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