MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 533

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
Serial Communication Controllers (SCCs)
7.10.20.10 BISYNC ERROR-HANDLING PROCEDURE. The BISYNC controller reports
message reception and transmission error conditions using the channel BDs, the error
counters, and the BISYNC event register. The modem interface lines can also be directly
monitored via the port C pins.
7.10.20.10.1 Transmission Errors. The following paragraphs describe various types of
BISYNC transmission errors.
Transmitter Underrun . When this error occurs, the channel terminates buffer transmission,
closes the buffer, sets the UN bit in the BD, and generates the TXE interrupt (if enabled).
The channel resumes transmission after the reception of the RESTART TRANSMIT com-
mand. Underrun cannot occur between frames or during a DLE-XXX pair in transparent
mode.
CTS Lost During Message Transmission . When this error occurs, the channel terminates
buffer transmission, closes the buffer, sets the CTS lost bit in the BD, and generates the TXE
interrupt (if enabled). The channel will resume transmission after reception of the RESTART
TRANSMIT command.
7.10.20.10.2 Reception Errors. The following paragraphs describe various types of
BISYNC reception errors.
Overrun Error . The BISYNC controller maintains an internal FIFO for receiving data. The CP
begins programming the SDMA channel (if the data buffer is in external memory) and updat-
ing the CRC when the first byte is received into the FIFO. If a FIFO overrun occurs, the
BISYNC controller writes the received data byte to the internal FIFO over the previously
received byte. The previous character and its status bits are lost. Following this, the channel
closes the buffer, sets the OV-bit in the BD, and generates the RX interrupt (if enabled). The
receiver then enters hunt mode immediately.
CD Lost During Message Reception . When this error occurs, the channel terminates mes-
sage reception, closes the buffer, sets the carrier detect lost bit in the BD, and generates the
RX interrupt (if enabled). This error has the highest priority; the rest of the message is lost,
and no other errors are checked in the message. The receiver then enters hunt mode imme-
diately.
Parity Error . When this error occurs, the channel writes the received character to the buffer
and sets the PR bit in the BD. The channel terminates message reception, closes the buffer,
sets the PR bit in the BD, and generates the RX interrupt (if enabled). The channel also
increments the PAREC, and the receiver enters hunt mode immediately.
CRC Error . The channel updates the CR bit in the BD every time a character is received with
a byte delay (eight serial clocks) between the status update and the CRC calculation. When
using control character recognition to detect the end of the block and cause the checking of
the CRC that follows, the channel closes the buffer, sets the CR bit in the BD, and generates
the RX interrupt (if enabled).
7.10.20.11 BISYNC MODE REGISTER (PSMR). Each BISYNC mode register is a 16-bit,
memory-mapped, read-write register that controls SCC operation. The term BISYNC mode
MC68360 USER’S MANUAL
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