MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 787

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Applications
The test logic is comprised of features that include the boundary scan register and is
accessed through the test access port (TAP).
9.7.1 Board Layout
The test equipment interfaces to the board through a test bus, with the tester acting as a test
bus master. This bus is comprised of the boundary scan signals and consists of one or sev-
eral parallel signal paths. Although different architectures are described in the JTAG stan-
dard document, this application shows only one serial connection. As shown in Figure 9-22,
one data signal loop is created with relevant device. The test data in (TDI) signal enters the
device and exits the device as test data out (TDO) at the other end of the shift register. In
addition, a clock signal (TCK) and a mode signal (TMS) are distributed to all devices in par-
allel.
An example of a board designed with the boundary scan path architecture is shown in Figure
9-22. Most devices, like device 2 through device 5, are included in the loop. Other devices
such as memories can be tested directly from a microprocessor. Usually, the board will also
contain small logic functions or analog ICs that do not contain boundary scan logic.
Once the board is tested with the test equipment, it is typically stored until it is installed in
the final system. This storage time is comprised of warehouse and shipping time. How then
can the board be retested before it begins to interact with a larger system in the end appli-
cation? This is of particular importance in telecommunication systems with distributed intel-
ligence, since an error can propagate throughout the entire system if one node is
malfunctioning.
Today, almost every board design includes some kind of processor or controller. This con-
troller can be used as the test bus master to perform a board test using an existing boundary
scan path. The following paragraphs describe how this concept can be achieved using the
QUICC as the board controller.
9-67
2. Testing of the device itself.
3. Observation or modification of the activity on the board.
Freescale Semiconductor, Inc.
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Go to: www.freescale.com