MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 640

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Peripheral Interface (SPI)
completed transmission. In addition, the current Rx BD that is used to receive data is closed
after the transmission completes, even if the receive buffer is not full. Thus, the user does
not need to provide receive buffers of the same length as the transmit buffers.
If the SPI is the only master in a system, then the SPISEL pin can be used as a general-
purpose I/O, and the internal SPISEL signal to the SPI will always be forced inactive inter-
nally, eliminating the possibility of a multi-master error.
7.12.4.2 SPI SLAVE MODE. When the SPI functions in slave mode, the SPI receives mes-
sages from an SPI master and, in turn, sends back a simultaneous reply. The SPISEL pin
must be asserted before receive clocks will be recognized. Once SPISEL is asserted, the
SPICLK pin becomes an input from the master to the slave. SPICLK may be any frequency
from DC to the BRGCLK/2 (i.e., 12.5 MHz for a 25-MHz system).
Before the data exchange, the CPU32+ core writes the data to be transmitted into a data
buffer, configures a Tx BD with its R-bit set, and configures one or more Rx BDs. The
CPU32+ core should then set the STR bit in the SPCOM to enable the SPI to prepare the
data for transmission and wait for the SPISEL pin to be asserted. Data is shifted out from
the slave on the SPIMISO pin and shifted in through the SPIMOSI pin. A maskable interrupt
is issued upon complete transmission or reception of a full buffer or after an error has
occurred (receive overrun, transmit underrun, out of receive buffers, etc.). The SPI will then
continue reception using the next Rx BD in the ring until it runs out of receive buffers or the
SPISEL pin is negated.
Transmission will continue until no more data is available to be transmitted or the SPISEL
pin is negated. If the SPISEL pin is negated prior to all the transmit data being transmitted,
transmission will cease, but the Tx BD will remain open. Further transmission from that point
will continue once the SPISEL pin is reasserted and SPICLK begins toggling. After complet-
ing transmission of characters in the Tx DB, the SPI will transmit ones if SPISEL is not
negated.
7.12.4.3 SPI MULTI-MASTER OPERATION. The SPI can operate in a multi-master envi-
ronment in which some SPI devices are connected on the same bus. In this configuration,
the SPIMOSI, SPIMISO, and SPICLK pins of all SPIs are connected together, and the
SPISEL input pins are connected separately. In this environment, only one SPI device can
work as a master at a time; all the others must be slaves. When the SPI is configured as a
master and its SPISEL input goes active (low), a multi-master error has occurred since more
than one SPI device is currently a bus master. The SPI sets the MME bit in the event regis-
ter, and a maskable interrupt is issued to the CPU32+ core. It also disables the SPI opera-
tion and the output drivers of the SPI pins.
The CPU32+ core should clear the EN bit the SPMODE before using the SPI again. After
the problems are corrected, the MME bit should be cleared, and the SPI should be enabled
with the same procedure as after a reset.
7-316
The user should note the maximum data rate supported on the
SPI is 500Kbps. The SPI can transfer a single character at much
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MC68360 USER’S MANUAL
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