MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 720

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Scan Chain Test Access Port
destructive configurations. The user must avoid situations in which the QUICC output driv-
ers are enabled into actively driven networks.
The QUICC includes on-chip circuitry to detect the initial application of power to the device.
Power-on reset (POR), the output of this circuitry, is used to reset both the system and scan
chainlogic. The purpose for applying POR to the scan chaincircuitry is to avoid the possibility
of bus contention during power-on. The time required to complete device power-on is power-
supply dependent. However, the scan chainTAP controller remains in the test-logic-reset
state while POR is asserted. The TAP controller does not respond to user commands until
POR is negated.
The QUICC features a low-power stop mode, which is invoked using a CPU instruction
called LPSTOP. The interaction of the scan chaininterface with low-power stop mode is as
follows:
8.6 NON-SCAN CHAIN OPERATION
In non-scan chain operation, there are two constraints. First, the TCK input does not include
an internal pullup resistor and should not be left unconnected to preclude mid-level inputs.
The second constraint is to ensure that the scan chaintest logic is kept transparent to the
system logic by forcing TAP into the test-logic-reset controller state, using either of two
methods. During power-up, POR forces the TAP controller into this state. After power-up is
concluded, TMS must be sampled as a logic one for five consecutive TCK rising edges. If
TMS either remains unconnected or is connected to V CC , then the TAP controller cannot
leave the test-logic-reset state, regardless of the state of TCK.
8-12
1. The TAP controller must be in the test-logic-reset state to either enter or remain in the
2. The TCK input is not blocked in low-power stop mode. To consume minimal power,
3. The TMS and TDI pins include on-chip pullup resistors. In low-power stop mode, these
low-power stop mode. Leaving the TAP controller in the test-logic-reset state negates
the ability to achieve low-power, but does not otherwise affect device functionality.
the TCK input should be externally connected to V CC or ground.
two pins should remain either unconnected or connected to V CC to achieve minimal
power consumption.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com