MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 375

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

7.6.4.6.4 Externally Recognizing IDMA Operand Transfers. There are several methods
to externally determine that a bus cycle is being executed by the IDMA:
7.6.4.7 BUS EXCEPTIONS. While the IDMA has the bus and is performing operand trans-
fers, it is possible for bus exceptions to occur.
In any computer system, the possibility exists that an error will occur during a bus cycle due
to a hardware failure, random noise, or an improper access. When an asynchronous bus
structure, such as that supported by the M68000 is used, it is easy to make provisions allow-
ing a bus master to detect and respond to errors during a bus cycle. The IDMA recognizes
the same bus exceptions as the CPU32+ core: reset, bus error, halt, and retry.
7.6.4.7.1 Reset. Upon an external reset, the IDMA immediately aborts the channel opera-
tion, returns to the idle state, and clears CSR and CMR (including the STR bit). If a bus cycle
is in progress when reset is detected, the cycle is terminated, the control and address/data
pins are three-stated, and bus ownership is released. The IDMA can also be reset by RST
in the CMR.
7.6.4.7.2 Bus Error. When a fatal error occurs during a bus cycle, a bus error exception is
used to abort the cycle and systematically terminate that channel’s operation. The IDMA ter-
minates the current bus cycle, signals an error in the CSR using either the BES or BED bit,
and signals an interrupt if the corresponding bit in the CMAR is set. The IDMA clears STR
and waits for a restart of the channel and the negation of BERR before starting any new bus
cycles. Any data that was previously read from the source into the DHR will be lost.
7.6.4.7.3 Retry. When HALT and BERR are asserted during a bus cycle, the IDMA termi-
nates the bus cycle, releases the bus, and suspends further operation until these signals are
negated. When HALT and BERR are negated, the IDMA will arbitrate for the bus, re-execute
the previous bus cycle, and continue normal operation.
1. The function code lines may be programmed to a unique function code that identifies
2. The BCLRO pin can be used to show when the bus request is made. BCLRO is ne-
3. The DACKx signal shows accesses to the peripheral device. DACKx will operate even
an IDMA transfer.
gated during the final access by the IDMA before relinquishing the bus.
in the internal request modes and will activate on either the source or destination bus
cycles, depending on the ECO bit in the CMR.
Any device that is the source or destination of the operand under
IDMA handshake control for single address transfers may need
to monitor BERR to detect a bus exception for the current bus
DACKx, which is used to control the transfer to or from the de-
vice.
Items 1 and 2 may also be used by the SDMA channels.
cycle. BERR terminates the cycle immediately and negates
Freescale Semiconductor, Inc.
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NOTE
NOTE
IDMA Channels