MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 932

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

MC68MH360 Product Brief
D.1.2 Serial Interface
D.1.3 System Interface
D.2 QUICC ARCHITECTURE OVERVIEW
The QUICC is 32-bit controller that is an extension of other members of the Motorola
M68300 family. Like other members of the M68300 family, the QUICC incorporates the inter-
module bus (IMB). (The MC68302 is an exception, having an M68000 bus on chip.) The IMB
provides a common interface for all modules of the M68300 family, which allows Motorola
to develop new devices more quickly by using the library of existing modules. Although the
IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the first
device to implement this option.
The QUICC consists of three modules: the CPU32+ core, the SIM60, and the CPM. Each
module uses the 32-bit IMB. The MC68360 QUICC block diagram is shown in Figure D-1.
D-2
• Serial Multiplexed (Full Duplex) Input/Output 2048, 1544 or 1536 Kbps PCM - High-
• Compatible with T1/DS1 24 Channel and CEPT/E1 32 Channel PCM Highway, ISDN
• Sub Channeling On Each Time-Slot
• Allows Independent Transmit and Receive Routing, Frame Syncs, Clocking
• Concatenation of Any, Not Necessarily Consecutive, Time Slots to Channels Indepen-
• Supports H0, H11, H12 ISDN - Channels
• Allows Dynamic Allocation of Channels
• Up to 3 Additional HDLC 64 Kbps Channels at 25 Mhz System Clock when in QMC
• Ethernet Support at 33 Mhz System Clock on One SCC when Operating in QMC Mode
• QUICC Powerful System Support Features: CPU32+, Slave Mode, 040 Companion,
• On-Chip Bus Arbitration for Serial DMAs with No Performance Penalty
• Efficient Bus Usage (No Bus Usage For Non-Active Channel, and for Active Channels
• Efficient Control of the Interrupts to the CPU
• Supports External Buffer Descriptors Table
• Using On-Chip Enlarged Dual-Port RAM for Parameter Storage
ways
Basic Rate, ISDN Primary Rate, User Defined
dently for Receive/Transmit
Mode
Memory Controller, 2xIDMA, SIM60 Watchdogs, Bus Monitors, Timers, Low Power
Modes, Breakpoint Logic, Interrupt Controller
that Have Nothing to Transmit)
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com