MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 608

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Management Controllers (SMCs)
W—Wrap (Final BD in Table)
I—Interrupt
CM—Continuous Mode
The following status bits are written by the CP after the received data has been into the asso-
ciated data buffer.
ID—Buffer Closed on Reception of Idles
BR—Buffer Closed on Reception of Break
FR—Framing Error
PR—Parity Error
OV—Overrun
Data Length
7-284
The buffer was closed due to the reception of the programmable number of consecutive
idle sequences.
The buffer was closed due to the reception of a break sequence.
A character with a framing error was received and is located in the last byte of this buffer.
A framing error is a character without a stop bit. A new receive buffer will be used for fur-
ther data reception.
A character with a parity error was received and is located in the last byte of this buffer. A
new receive buffer will be used for further data reception.
A receiver overrun occurred during message reception.
Data length is the number of octets that the CP has written into this BD’s data buffer. It is
written only once by the CP as the BD is closed.
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been filled.
1 = The RX bit in the event register will be set when this buffer has been completely
0 = Normal operation.
1 = The E-bit is not cleared by the CP after this BD is closed, allowing the associated
receive incoming data into the first BD in the table (the BD pointed to by RBASE).
The number of Rx BDs in this table is programmable and is determined only by the
W-bit and the overall space constraints of the dual-port RAM.
filled by the CP, indicating the need for the CPU32+ core to process the buffer. The
RX bit can cause an interrupt if it is enabled.
data buffer to be overwritten automatically when the CP next accesses this BD.
However, the E-bit will be cleared if an error occurs during reception, regardless of
the CM bit.
Freescale Semiconductor, Inc.
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MC68360 USER’S MANUAL
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