MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 84

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Bus Operation
The SIZ0 and SIZ1 outputs indicate the remaining number of bytes to be transferred during
the current bus cycle (see Table 4-3).
The number of bytes transferred during a write or read bus cycle is equal to or less than the
size indicated by the SIZx outputs, depending on port width and operand alignment. For
example, during the first bus cycle of a long-word transfer to a word port, the SIZx outputs
indicate that four bytes are to be transferred, although only two bytes are moved on that bus
cycle.
A0 and A1 also affect operation of the data multiplexer. During an operand transfer, A2-A31
indicate the long-word base address of that portion of the operand to be accessed; A0 and
A1 indicate the byte offset from the base. Table 4-4 lists the encoding of A0 and A1 and the
corresponding byte offset from the long-word base.
4-8
INCREASING
ADDRESSES
MEMORY
MULTIPLEXER
EXTERNAL
REGISTER
DATA BUS
ADDRESS
xxxxxxxx0
xxxxxxxx0
xxxxxxxx0
2
1
2
3
Figure 4-3. QUICC Interface to Various Port Sizes
D31–D24
BYTE 0
BYTE 0
BYTE 2
BYTE 0
BYTE 1
BYTE 2
BYTE 3
0P0
0
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SIZ1
0
1
1
0
8-BIT PORT
Table 4-3. SIZx Encoding
MC68360 USER’S MANUAL
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D23–D16
BYTE 3
BYTE 1
BYTE 1
ROUTING AND DUPLICATION
0P1
1
SIZ0
1
0
1
0
16-BIT PORT
D15–D8
BYTE 2
0P2
2
Byte
Word
3 Bytes
Long Word
Size
BYTE 3
D7–D0
0P3
3
32-BIT PORT
EXTERNAL BUS
INTERNAL TO
THE MC68360