MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 246

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
System Integration Module (SIM60)
The SIM60 has additional support of low-power modes. The clock synthesizer provides sys-
tem clocks to the SIM60 and other modules. This clock scheme supports low-power modes
for applications that use the baud rate generators and/or serial ports during the standby
mode. The main system clock can be changed dynamically (the slow-go option) while the
baud rate generators and serial ports work with a fixed frequency.
The breakpoint logic provides an internal breakpoint address register that allows hardware
breakpoints in a QUICC system. This function is especially useful during in-field debugging
activity when it is difficult to connect an in-circuit emulator or logic analyzer to the target
board.
The QUICC supports the slave mode. In this mode, the CPU32+ core on the QUICC is dis-
abled, and the QUICC functions as an intelligent peripheral. For instance, if the application
requires more serial channels than the QUICC provides, multiple QUICCs may be config-
ured onto the same system bus, one with its CPU enabled and the rest in slave mode. Alter-
natively, if the application needs additional CPU performance, the QUICC may function as
a companion chip to an MC68EC040 (or other M68040 family member). This is called
MC68040 companion mode. In this mode, the QUICC's glueless interface to the
MC68EC040 provides a two-chip MC68EC040 system solution. The MC68EC040 can also
control multiple QUICCs in slave mode. Finally, the QUICC slave mode may also support
an external MC68EC030 or other M68030 family member.
The EBI handles the transfer of information between the internal CPU32+ core and memory,
peripherals, or other processing elements in the external address space, or between an
external master and the QUICC RAM and registers. Section 4 Bus Operation describes the
bus operation, but the configuration control of the EBI is contained in this section.
The following functions are physically part of the SIM60, but are described in other places
in this manual.
The memory controller module provides glueless interfaces to many types of memory and
peripherals. It contains up to 8 general-purpose chip selects with up to 15 wait states each
and a full DRAM controller that controls up to 8 DRAM banks. See 6.10 Memory Controller
for further information.
The QUICC dynamically interprets the bus port size of an addressed device during each bus
cycle, allowing operand transfers to/from 8-, 16-, and 32-bit ports. The DSACK signals are
used to signify the data port size. Dynamic bus sizing can result in reduced system cost. For
instance, an 8-bit boot EPROM may be used with 16-bit peripherals and 32-bit DRAM.
Dynamic bus sizing also allows a programmer to write code that is not bus-width specific.
For a discussion on dynamic bus sizing see Section 4 Bus Operation.
The QUICC is designed to allow external bus masters the opportunity to access the inter-
module bus (IMB). This design has two main purposes. First, the RAM and peripherals on
the QUICC can be directly accessed, if desired, by an external master. Second, the external
master can use QUICC resources, such as the chip-select generation logic and DRAM con-
troller. See Section 4 Bus Operation for further discussion.
6-2
MC68360 USER’S MANUAL
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