MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 571

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

SCC Base + 30
SCC Base + 34
SCC Base + 38
SCC Base + 3C
SCC Base + 40
SCC Base + 44
SCC Base + 46
SCC Base + 48
SCC Base + 4A
SCC Base + 4C
SCC Base + 4E
SCC Base + 50
SCC Base + 52
SCC Base + 54
SCC Base + 56
SCC Base + 58
SCC Base + 5A
SCC Base + 5C
SCC Base + 5E
SCC Base + 60
SCC Base + 64
SCC Base + 68
SCC Base + 6C
SCC Base + 70
SCC Base + 72
SCC Base + 74
SCC Base + 76
SCC Base + 78
SCC Base + 7A
SCC Base + 7C
SCC Base + 7E
SCC Base + 80
SCC Base + 84
SCC Base + 88
SCC Base + 8C
SCC Base + 90
SCC Base + 92
SCC Base + 94
SCC Base + 96
SCC Base + 98
SCC Base + 9A
SCC Base + 9C
Address
Table 7-11. Ethernet-Specific Parameters
TBUF0.data0
TBUF0.data1
TBUF1.data0
TBUF1.data1
PADDR1_M
Freescale Semiconductor, Inc.
TBUF0.rba0
TBUF0.bcnt
PADDR1_H
TBUF1.rba0
TBUF1.bcnt
PADDR1_L
BOFF_CNT
TBUF1.crc
TBUF0.crc
RFBD_ptr
RET_Lim
DMA_cnt
TFBD_ptr
TLBD_ptr
C_MASK
GADDR1
GADDR2
GADDR3
GADDR4
C_PRES
RET_cnt
MINFLR
IADDR1
IADDR2
IADDR3
IADDR4
CRCEC
MAXD1
MAXD2
MAX_b
TX_len
DISFC
For More Information On This Product,
MAXD
Name
ALEC
PADS
MFLR
P_Per
MC68360 USER’S MANUAL
Go to: www.freescale.com
Width
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Long
Long
Long
Long
Long
Long
Long
Long
Long
Long
Long
Long
Long
Preset CRC
Constant MASK for CRC
CRC Error Counter
Alignment Error Counter
Discard Frame Counter
Short Frame PAD character
Retry Limit Threshold
Retry Limit Counter
Maximum Frame Length Register
Minimum Frame Length Register
Max DMA1 Length Register
Max DMA2 Length Register
Rx Max DMA
Rx DMA Counter
Max BD Byte Count
Group Address Filter 1
Group Address Filter 2
Group Address Filter 3
Group Address Filter 4
Save Area 0 - Current Frame
Save Area 1 - Current Frame
Physical Address 1 (LSB)
Physical Address 1
Physical Address 1 (MSB)
Persistence
Rx First BD Pointer
Tx First BD Pointer
Tx Last BD Pointer
Save Area 0 - Next Frame
Save Area 1 - Next Frame
Tx Frame Length Counter
Individual Address Filter 1
Individual Address Filter 2
Individual Address Filter 3
Individual Address Filter 4
Backoff Counter
Description
Serial Communication Controllers (SCCs)
2
$FFFFFFFF
$DEBB20E3
15 dec
1518 dec
64 dec
1518 dec
1518 dec
User Writes