PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 128
PNX1501E
Manufacturer Part Number
PNX1501E
Description
Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1501E.pdf
(819 pages)
Specifications of PNX1501E
Product
DSPs
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOT-795
Minimum Operating Temperature
0 C
Lead Free Status / Rohs Status
Details
Other names
PNX1501E,557
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Philips Semiconductors
Volume 1 of 1
8. Miscellaneous
12NC 9397 750 14321
Product data sheet
Several other system MMIO registers are described in the following paragraphs and
detailed in the next
•
•
•
•
By default PCI_INTA_N is an input/output pin used in open drain mode for the
PCI bus. When a host CPU wants to assert an interrupt to the TM3260 it asserts
the PCI_INTA_N low. Similarly if TM3260 wants to notify a host CPU of an
interrupt it can assert low the PCI_INTA_N pin by programming the PCI_INTA
MMIO register.
The 8 SCRATCH MMIO registers are mainly used for debug purpose. Since they
are not reset by the external POR_IN_N or RESET_IN_N signals they can be
used for post-mortem system crash to retain some critical or debug values.
Event timestamping for the SPDI interface comes with a diversity of
requirements. To keep PNX15xx Series as a programmable system, a system
multiplexer is implemented to select which event or signal to timestamp. The
multiplexer is controlled by the SPDI_MUX_SEL MMIO register. The different
selectable signals coming from the SPDI module are displayed in
The SPARE_CTRL MMIO register is reserved for future usage.
Rev. 2 — 1 December 2004
Section
8.1:
Chapter 3: System On Chip Resources
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
Section
8.1.
3-26
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