PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 351

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
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Product data sheet
2.2 Architecture
The basic block diagram of the QVCP is illustrated in
accommodates 2 symmetrical layers, which suggest 2 image surfaces with
independent characteristics such as pixel data format, color space, size and position
on the final composite image. Each of these layers is tied into the memory access
infrastructure of the PNX15xx Series via an independent DMA read interface. A layer
(or a layer module, as it is called) is responsible for producing a valid pixel for every
display coordinate. Both layer modules, as mentioned before, are identical, and so,
there are no restrictions as to how each layer may be utilized: 2 video layers, 2
graphics layers, or 1 graphic + 1 video layer are examples of some of the
combinations that can be achieved. However, as described later, there are some
restrictions on the image improvements that can be applied per surface. A wide
variety of RGB, YUV, and alpha blend formats are supported. Each layer, as detailed
later, can perform a variety of video-processing functions such as color space
conversion, 4:4:4 to 4:2:2 down-filtering and 4:2:2 to 4:4:4 up-sampling, color- and
chroma key extraction, etc. It should be noted that “region-based graphics” is not
supported at the hardware level; software must generate one uniform color depth
surface if an application requires region based graphics.
The QVCP is architected using the concept of virtual identical layers with a
common resource pool. Each layer is built as a skeleton which contains only the
essentialprocessing blocks. The remaining processing blocks --- the more exotic ones
responsible for picture enhancement, for example --- are part of the pool
resources.The principal assumption, in defining the QVCP architecture, is that there
is no use-case which requires all of the features to be active in all of the layers at the
same time. For any particular use-case, there will be a specific selection of features
required in each layer. All layers can make use of pool resources. There is no specific
order or assignment of the pool resources to the specific layers. However, prior to
using QVCP in the context of a specific application scenario, it is required to assign
resources from the pool to specific layers. This is done via a set of global QVCP
resource-allocation registers.
In addition to the symmetric layer structure, the QVCP contains, as mentioned before,
a set of (special) image processing functions which are located outside of the layers
in a resource pool. The pool-resource concept takes into account the fact that
software drivers would like to access the layers in a symmetrical unified fashion. The
features used in a certain display scenario are however not symmetrically distributed
among the layers at all. For a given application scenario, there is no case when every
layer uses all its resources. Therefore theses features which are never used by all
layers at the same time are located in the resource pool. Hence, the pool contains
only a number of functional units of the same kind which is smaller than the total
number of layers.
Attached to each layer is a mixer which acts as a three-port image combination
module, combining the image coming from the layer attached to the mixer with the
image coming from the previous mixer. The resultant image is forwarded to the next
mixer. This mixer cascade implies a certain layer, and therefore a certain image,
order on the final display surface.
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Figure
PNX15xx Series
2. The front-end part
Chapter 11: QVCP
11-5