PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 310

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
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Product data sheet
If pre-empting of the MTL transaction is not allowed, then all DDR bursts from one MTL transaction are treated the same. So if the
first DDR burst is (not) for free then the other DDR bursts for the same MTL transactions will also be (not) for free. If pre-emption of
the MTL transaction is allowed, then the ‘for free’ decision is made separately for each DDR burst.
There are two mechanisms available in the arbitration: windows and account budgets.
Windows provide the basic means to allocate DDR bandwidth. A window is defined in
terms of DDR controller clock cycles. Windows are defined for DMA traffic
(HRT_WINDOW) and CPU traffic (CPU_WINDOW), and they alternate with each
other in time. During an HRT_WINDOW, the DMA traffic is given priority by the
arbitration scheme. During a CPU_WINDOW, the CPU traffic is given priority by the
arbitration scheme.
As implied by the names CPU_WINDOW and HRT_WINDOW, windows have been
introduced to divide DDR bandwidth between CPU traffic and Hard Real-Time (HRT)
DMA traffic. Typically, in an SOC a third type of traffic is present as well: Soft
Real_time (SRT) DMA traffic. This type of traffic usually has less hard real-time
constraints than HRT DMA traffic i.e., the bandwidth requirements can be averaged
over a much larger time period (several windows) than with HRT. However, it is still
necessary to ensure that this type of traffic receives DDR memory bandwidth. To this
end, a CPU account is introduced.
The CPU account limits (budgets) the memory bandwidth consumption by the CPU
traffic to ensure that SRT DMA traffic receives enough memory bandwidth. The CPU
account is defined by CPU_RATIO, CPU_LIMIT, CPU_CLIP and CPU_DECR.
The value CPU_RATIO controls how much bandwidth the CPU can get. The value
CPU_LIMIT controls how many DDR bursts the CPU can take back-to-back before
the CPU is out of budget. The value CPU_CLIP controls how much debt the CPU is
allowed to build up. CPU_DECR is made programmable so that the accuracy of the
accounting can be increased. This is especially needed when using dynamic ratios
(see
When the internal account exceeds CPU_LIMIT, DMA traffic is given higher priority
than CPU traffic, independent of which window is active. The internal account is a
saturated counter, that is, it will not wrap around on an underflow or overflow. For
every DDR controller memory clock cycle, the internal counter is decremented by
CPU_DECR. Whenever a CPU DDR burst is started, the internal counter is
incremented by an amount equal to the amount of data transfer cycles, plus the value
of CPU_RATIO, except when a CPU MTL transaction is ‘for free’.
A CPU MTL transaction is for free if it starts while the account value is above the
CPU_CLIP value
amount equal to the amount of data transfer cycles, without the CPU_RATIO. The
CPU_CLIP value should always be set equal or higher than CPU_LIMIT, otherwise
CPU_LIMIT would never be reached.
By means of the accounting mechanism, the CPU bandwidth can be budgeted. In the
CPU_WINDOW a CPU normally has priority over DMA. For every clock cycle the
CPU account gets funded with CPU_DECR. For every CPU DDR burst, the costs of
that burst, defined as CPU_RATIO plus data transfer cycles, are accounted for. When
the CPU account runs out of budget (account value above CPU_LIMIT), then DMA
will get priority over the CPU.
Section
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Rev. 2 — 1 December 2004
. If a DDR burst is for free, then the account gets incremented by an
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 9: DDR Controller
PNX15xx Series
9-4