PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 673

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 2: LAN100 Registers
12NC 9397 750 14321
Product data sheet
Bit
6:0
Offset 0x07 200C
31:15
14:8
7
6:0
Offset 0x07 2010
31:14
13:8
7:4
3:0
Offset 0x07 2014
31:16
15:0
Offset 0x07 2018
The SUPP register is only relevant if an SMII, RMII, PMD or ENDEC interface is provided to the PHY.
31:16
Symbol
BACK_TO_BACK_
INTER_PACKET_GAP
-
NON_BACK_TO_
BACK_INTER_
PACKET_GAP_PART_1
-
NON_BACK_TO_
BACK_INTER_
PACKET_GAP_PART_2
-
COLLISION_WINDOW
RETRANSMISSION_
MAXIMUM
-
MAXIMUM_FRAME_
LENGTH
-
Non Back-to-Back Inter-Packet-Gap Register (IPGR)
Collision Window / Retry Register (CLRT)
Maximum Frame Register (MAXF)
PHY Support Register (SUPP)
…Continued
Acces
s
R/W
0
0
0
0x12
-
R/W
-
R/W
-
R/W
-
Value
0
-
R/W
-
R/W
0
0x37
0
0xF
0
0x0600
0
Rev. 2 — 1 December 2004
Description
This is a programmable field representing the nibble time offset of
the minimum possible period between the end of any transmitted
packet, to the beginning of the next. In full-duplex mode, the
register value should be the desired period in nibble times minus 3.
In half-duplex mode, the register value should be the desired period
in nibble times minus 6. In full-duplex, the recommended setting is
0x15 (21 decimal), which represents the minimum IPG of 0.96 ms
(in 100 Mb/s) or 9.6 ms (in 10 Mb/s). In half-duplex the
recommended setting is 0x12 (18 decimal), which also represents
the minimum IPG of 0.96 ms (in 100 Mb/s) or 9.6 ms (in 10 Mb/s).
Unused
This is a programmable field representing the optional carrierSense
window referenced in IEEE 802.3 section 4.2.3.2.1 titled “Carrier
Deference”. If carrier is detected during the timing of IPGR1, the
MAC defers to carrier. If, however, carrier becomes active after
IPGR1, the MAC continues timing IPGR2 and transmits, knowingly
causing a collision, thus ensuring fair access to the medium. Its
range of values is 0x0 to IPGR2.
Unused
This is a programmable field representing the Non-Back-to-Back
Inter-Packet-Gap. The default is 0x12 (18 decimal), which
represents the minimum IPG of 0.96 ms (in 100 Mb/s) or 9.6 ms (in
10 Mb/s).
Unused
This is a programmable field representing the slot time or collision
window during which collisions occur in properly configured
networks. Since the collision window starts at the beginning of
transmission, the preamble and SFD is included. Its default of 0x37
(55 decimal) corresponds to the count of frame bytes at the end of
the window.
Unused
This is a programmable field specifying the number of
retransmission attempts following a collision before aborting the
packet because of excessive collisions. The Standard specifies the
attemptLimit to be 0xF (15 decimal).
Unused
This field’s reset value is 0x0600, which represents a maximum
receive frame of 1536 octets. An untagged maximum size Ethernet
frame is 1518 octets. A tagged frame adds four octets for a total of
1522 octets. If a shorter maximum length restriction is desired,
program this 16-bit field.
Unused
Chapter 23: LAN100 — Ethernet Media Access Controller
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
23-11