PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 235

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 8: Registers Description
12NC 9397 750 14321
Product data sheet
Bit
PCI Control Registers
This register must be initialized before any PCI cycles will be entertained. The boot loader is expected to load the values at
boot time. Write once by boot loader, otherwise read only. Because this register is “written once” the bit fields are designated
“R/W1.” An unlock is available to update this register if necessary. A write of “CA” to bits [7:0] of the unlock_setup register
will allow one additional write to the setup register before locking again
Offset 0x04 0010
31
30
29
28
27
26
25
24
23
22
21
Symbol
Reserved
dis_reqgnt
dis_reqgnt_a
dis_reqgnt_b
d2_support
d1_support
Reserved
en_ta
en_pci2mmi
en_xio
base18_prefetchable
PCI Setup
Table 7: PCI Configuration Register Summary
The following table is a summary of all the registers in this module.
Bit
0x000C
0x0010
0x0014
0x0018
0x001—
0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
Acces
s
R
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
Symbol
Latency Timer/ Cache
Line size
Base Address 10
Base Address 14
Base Address 18
Reserved
Subsystem ID
Reserved
Capability Pointer
Reserved
INTR
pmc
pwr_state
Value
0
0
0
0
1
1
0
0
1
1
0
Rev. 2 — 1 December 2004
Description
Disable use of REQ/GNT when using internal arbiter. These pins
may be released for other uses when using an internal arbiter and
no external PCI masters are used in the system.
Disable use of REQ_A/GNT_A when using internal arbiter. These
pins are not used when using an external harborer.
Disable use of REQ_B/GNT_B when using internal arbiter. These
pins are not used when using an external arbiter.
Support for D2 power state
Support for D1 power state
Terminate restricted access attempt with target abort (otherwise,
ignore writes, return 0 on read).
Enable memory hwy interface.
Enable XIO functionality.
PCI base address 18 is a prefetchable memory aperture.
Description
Latency Timer, Cache Line Size.
Base Address, memory
Base Address, memory — MMIO
Base Address, memory — XIO
Subsystem ID and Subsystem Vendor ID
Capabilities Pointer Register
Interrupt Line, Interrupt Pin, Min_Gnt, MAX_Lat
Power management Capability
Power Management control
…Continued
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 7: PCI-XIO Module
PNX15xx Series
7-23