PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 30

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 4: PNX1500 Interface
12NC 9397 750 14321
Product data sheet
Pin Name
PCI_SYS_CLK
Miscellaneous System Interface
POR_IN_N
RESET_IN_N
SYS_RST_OUT_N
RESERVED
Main Memory Interface (DDR SDRAM controller)
Refer to
MM_CLK
MM_CLK_N
MM_CS1_N
MM_CS0_N
MM_RAS_N
MM_CAS_N
MM_WE_N
MM_CKE
AVREF
Section 10.3 on page 1-45
BGA
Ball
AB23 BPT3MCHDT5V
E25
A11
D10
M1
M2
M4
C7
V4
N3
N2
L3
L1
J2
Pad
Type
SSTLREFGEN
BPT3MCHT5V
BPT3MCHT5V
BPX2T14MCP
BPX2T14MCP
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLCLKIO
SSTLCLKIO
for board design guidelines
Rev. 2 — 1 December 2004
I/O
Type
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
GPIO
#
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P Description
U This clock is intended for use as the PCI clock in
U PNX1500 Power On Reset input. Asserting this
U PNX1500 reset input. Asserting this input low
U Active low peripheral reset output. This output is
D Reserved for future expansion. It has to be left
-
-
-
-
- Row address strobe. It is active low.
- Column address strobe. It is active low.
- Write enable. It is active low
- Clock enable output to DDR SDRAMs.
- Voltage reference.
simple PNX1500 PCI configurations. It outputs a
33.23 MHz clock. A board level 27-33
resistor is recommended to reduce ringing.
input low triggers the hardware reset function of the
PNX1500 (including the JTAG state machine).
This pin can typically be connected to an on-board
reset upon voltage drop. It is active low. Upon
asserting this reset input, the PNX1500 asserts
SYS_RST_OUT_N to reset the attached peripheral
chips. This pin can also be tied to the PCI_RST_N
signal in PCI bus systems. This pin is 5 V tolerant
input.
triggers the hardware reset function of the
PNX1500 (This does not reset the JTAG state
machine). Upon asserting this reset input,
PNX1500 asserts SYS_RST_OUT_N to reset
attached peripheral chips. This pin can also be tied
to the PCI_RST_N signal in PCI bus systems.
With respect to the POR_IN_N reset pin, this pin
can be used has a warm reset. For most
applications, both reset pins can be tied together. it
is active low. This pin is 5 V tolerant input.
asserted upon any PNX1500 reset (hardware,
watchdog timer or software), and de-asserted by
PNX1500 system software. It is intended to be used
as a reset for external peripherals.
unconnected at the board level for normal
operation. It was named RESERVED2.
DDR SDRAM Output Clock. Refer to
on page 1-45
Chip select for DDR SDRAM. It is active low.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 1: Integrated Circuit Data
for board level connections.
PNX15xx Series
Section 10.3
series
1-4