PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 140

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
Figure 3:
SYS_RST_OUT_N
time_out_int_pls
watchdog_count
watchdog_reset
interrupt_count
sys_rst_out_n
clk_dtl_mmio
Watchdog in Interrupt Mode
1: The interrupt is enabled then the watchdog count and the interrupt count registers are programmed.
2: The interrupt count is happening.
3: The interrupt count reaches the programmed value and a time out interrupt pulse is issued to the CPU.
4: The watchdog counter begins.
5: The interrupt has not been cleared. A watchdog reset is issued.
6: The internal and external resets are asserted.
peri_rst_n
2.3 The Software Reset
2.4 The External Software Reset
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Here once the interrupt is asserted then the first counter is reset to zero
The counters operate with the DCS clock also called MMIO clock (clk_dtl_mmio).
The following
The software reset is started by writing a 0x1 to RST.CTL.DO_SW_RST bit.
The reset follows then the regular software reset timing,
The signal sys_rst_out_n signal can be asserted by writing a 0x1 to the
RST_CTL.ASSERT_SYS_RST_OUT bit.
The signal sys_rst_out_n signal can be de-asserted by writing a 0x1 to the
RST_CTL.REL_SYS_RST_OUT bit.
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5. If step 4 does not occur before the count reaches the WATCHDOG_COUNT
6. A write with 0x1 to INTERRUPT_CLEAR stops the interrupt counter and restarts
7. The interrupt counter reaches the INTERRUPT_COUNT value, the PNX15xx
value an interrupt is issued to the TM3260 CPU and the second internal counter
(the interrupt counter) starts. The internal watchdog counter is reset and waits
the interrupt to be cleared.
the watchdog counter. Therefore for continuous watchdog timer operation start
back at step 5).
Series system reset is asserted.
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Figure 3
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Rev. 2 — 1 December 2004
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© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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PNX15xx Series
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3.2.
Chapter 4: Reset
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