PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 342

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
Figure 3:
Power Sequencing State Machine Block Diagram
3.2.1 IDLE state
3.2.2 DCEN state
BLEN
calculated using a 26-bit counter that is controlled by the state machine. This counter
runs on the 27 MHz clock (the input PNX15xx Series crystal). The state machine is
shown in
After reset, the state machine comes up in the IDLE state. In this state, when the
lcd_enbl signal (which is asserted when both lcd_if_en and start_pud_seq bits are
set) is asserted, the power up sequence is started by asserting the TFTVDDON
signal and loading the counter with PWREN_DCE_DELAY that is set in the
LCD_SETUP register. The counter starts to count down after it is loaded.
If the lcd_enbl is de-asserted in the IDLE state, then the state machine goes to the
PEPED state, de-asserts the TFTVDDON signal and loads the counter with
PWR_EN_PWREN_DELAY value.
If the lcd_enbl is still asserted when the counter decrements to zero, then the state
machine goes to DCEN state and asserts the ‘dce’ signal. It also loads the counter
with DCE_BKLT_DELAY value.
In the DCEN state, when the counter reaches zero and lcd_enbl is still asserted, then
the state machine transitions to the BLEN state and asserts the TFTBKLTON signal.
This completes the power up sequence.
If the lcd_enbl signal is de-asserted when ‘dce’ signal is still asserted, then the ‘dce’
signal is de-asserted and the counter is loaded with DCE_PWREN_DELAY value.
There is no state transition.
If the counter reaches zero with both the dce and lcd_enbl signal de-asserted, the
state machine transitions to the PEPED state. During this transition, the TFTVDDON
signal is de-asserted and the counter is loaded with PWREN_PWREN_DELAY value.
!lcd_enbl && cnt_done
lcd_enbl && cnt_done
Figure
3.
Rev. 2 — 1 December 2004
DCEN
!lcd_enbl && cnt_done && !dce
IDLE
cnt_done
lcd_enbl_neg
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PEPED
Chapter 10: LCD Controller
PNX15xx Series
10-4