PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 671

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 2: LAN100 Registers
12NC 9397 750 14321
Product data sheet
Bit
MII Interface Registers
Offset 0x07 2000
31:16
15
14
13:12
11
10
9
8
7:5
4
3
2
1
0
Offset 0x07 2004
31:16
14
13
Symbol
-
SOFT_RESET
SIMULATION_RESET
-
RESET_PEMCS/Rx
RESET_PERFUN
RESET_PEMCS_Tx
RESET_PETFUN
-
LOOPBACK
TX_FLOW_CONTROL
RX_FLOW_CONTROL
PASS_ALL_RECEIVE_
FRAMES
RECEIVE_ENABLE
-
EXCESS_DEFER
BACK_PRESSURE
MAC Configurationuration Register 1 (MAC1)
MAC Configuration Register 2 (MAC2)
Acces
s
-
R/W
R/W
-
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
Value
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 2 — 1 December 2004
Description
Unused
Setting this bit puts all modules within the MII Interface into the reset
state. MII Interface registers are not reset. It has no effect upon
LAN100 components other than the MII Interface. Clearing this bit
restores the MII Interface to operation. Its default value is 1 (reset).
Setting this bit will reset the random number generator within the
Transmit function of the MII Interface.
Unused
Setting this bit puts the MAC Control Sublayer / Rx domain logic into
the reset state.
Setting this bit puts the Receive Function logic in the reset state.
Setting this bit puts the MAC Control Sublayer / Tx domain logic in
the reset state.
Setting this bit puts the MII Interface Transmit function logic in the
reset state.
Unused
Setting this bit causes the MAC Transmit interface to be looped
backed to the MAC Receive interface. Clearing this bit results in
normal operation.
When set, PAUSE Flow Control frames are allowed to be
transmitted. When cleared, Flow Control frames are blocked.
When set, the MAC acts upon received PAUSE Flow Control
frames. When cleared, received PAUSE Flow Control frames are
ignored.
When set, the MAC will indicate PASS CURRENT RECEIVE
FRAME for all frames regardless of type (normal vs. Control).
When cleared, the MAC deasserts PASS CURRENT RECEIVE
FRAME for valid Control frames.
Set this bit to enable receiving frames. Internally, the MAC
synchronizes this control bit to the incoming receive stream and
outputs SYNCHRONIZED RECEIVE ENABLE, to be used by the
host system to qualify receive frames.
Unused
When set, the MAC will defer to carrier indefinitely as per the
Standard
deferral limit is reached, and will provide feedback to the host
system.
When set, the MAC after incidentally causing a collision during back
pressure will immediately retransmit without backoff, reducing the
chance of further collisions and ensuring transmit packets get sent.
Chapter 23: LAN100 — Ethernet Media Access Controller
[1].
When cleared, the MAC will abort when the excessive
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
23-9