PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 143

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
4. Register Definitions
Table 1: RESET Module
12NC 9397 750 14321
Product data sheet
Bit
Reset Module
Offset 0x06,0000
31:3
2
1
0
Offset 0x06,0004
Remark: RST_CTL is set on every time an hardware or software reset occurs.
31:2
1:0
Offset 0x06,0008
31:0
Offset 0x06,000C
31:0
Offset 0x06,0FE0
31:1
0
Offset 0x06,0FE4
31:1
0
Offset 0x06,0FE8
31:1
Symbol
Unused
DO_SW_RST
REL_SYS_RST_OUT
ASSERT_SYS_RST_O
UT
Unused
RST_CAUSE
WATCHDOG_COUNT
INTERRUPT_COUNT
Unused
WATCHDOG_INTERRU
PT
Unused
WATCHDOG_INTERRU
PT_ENABLE
Unused
WATCHDOG_COUNT
INTERRUPT_COUNT
RST_CTL
RST_CAUSE
INTERRUPT STATUS
INTERRUPT_ENABLE
INTERRUPT_CLEAR
Acces
s
W
W
W
W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Value
-
0
0
0
-
N/A
0
0
-
0
-
0
-
Rev. 2 — 1 December 2004
Description
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 = No action
1 = Do Software Reset.
0 = No action
1 = Release System Reset of External Peripherals.
0 = No action
1 = Do System Reset of External Peripherals.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Reset Cause register:
00 = Cause is External System Reset, RESET_IN_N.
01 = Cause is Software System Reset.
10 = Cause is External System Reset, POR_IN_N
11 = Cause is watchdog time-out.
Note if multiple resets occur then only the one that is highest in the
above order will be registered. As an example RESET_IN_N (00)
and POR_IN_N (10) are both asserted. A read would return “10”
Value to count to in order to either assert an interrupt (interrupt
mode) or a reset (non interrupt mode)
Value to count to after the interrupt is asserted before asserting the
system reset
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
1: watchdog interrupt is asserted
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
1: interrupt enabled
0: interrupt NOT enabled
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
Chapter 4: Reset
4-9