PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 544

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
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Product data sheet
3.3.2 Transparent Mode
3.4.1 DMA Error Conditions
3.4 Errors and Interrupts
IEC-60958 Parity
The parity bit, or P bit in
value should be set such that bit cells 4 to 31 inclusive contain an even number of
ones (and hence even number of zeroes). The P bit is bi-phase mark encoded using
the same method as for all other bits.
IEC-60958 Memory Data Format
The system software must prepare a memory data structure that instructs the SPDIF
block hardware to generate correct IEC-60958 blocks. This data structure consists of
32-bit words with the content described in Table 5.3:
Table 2: SPDIF Subframe Descriptor Word
The data structure for a block consists of 384 of these 32-bit descriptor words, one for
each subframe of the block, with the correct B, M, W values. All data content,
including the U, C and V flag are fully under control of the software that builds each
block.
A DMA buffer handed to the hardware is required to be a multiple of 64 bytes in
length. It can contain 1 or more complete blocks, or a block may straddle DMA buffer
boundaries. The 64 byte length will result in DMA buffers that contain a multiple of 16
subframes.
When SPDO is set to operate in transparent mode, it takes all 32-bits of the memory
data and shifts them out as is, without bi-phase mark encoding, parity generation or
preamble insertion.
Two transparent modes are provided, as determined by the TRANS_MODE field in
SPDO_CTL: LSB first and MSB first.
One bit of memory data is transmitted for each DDS clock.
The 32-bit memory word is constructed according to the same rules for byte ordering
as in
Two types of errors can occur during DMA operation.
Bits
31 (msb)
30..4
3..0 (lsb)
Section IEC-60958 Memory Data Format
Definition
This bit must be a ‘0’ for future compatibility.
Data value for bits 4..30 of the subframe, exactly as they are to be
transmitted. Hardware will perform the bi-phase mark encoding and Parity
generation.
0000 - generate a B preamble
0001 - generate an M preamble
0010 - generate a W preamble
0011 .. 1111 reserved for future
Rev. 2 — 1 December 2004
Figure
1, is computed by the SPDIF Out hardware. The P bit
above.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 17: SPDIF Output
PNX15xx Series
17-6