PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 690

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
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Product data sheet
be 7. For each element of the descriptor array, there is an associated status field in
the status array. The base address of the status array is stored in the RxStatus
register. During operation, that is, when the Receive Datapath is enabled, the
RxDescriptor, RxStatus and RxDescriptorNumber registers should not be modified.
The base address of the descriptor array as stored in the RxDescriptor register
should be aligned on an 8-byte address boundary. The status array base address in
the RxStatus register must be aligned on an 8-byte address boundary.
The RxConsumeIndex and RxProduceIndex registers contain counters that start at 0
and wrap back around to 0 when they equal RxDescriptorNumber. The
RxProduceIndex indexes the descriptor that will be filled by the next packet received
by the LAN100. It is incremented by the hardware. The RxConsumeIndex is
programmed by software, and is the index of the next descriptor that the software
receive driver is going to process. If RxProduceIndex == RxConsumeIndex, then the
receive buffer is empty. If RxProduceIndex == RxConsumeIndex – 1 then the receive
buffer is full, and newly received data would generate an overflow unless the software
driver frees up some descriptors.
Each Receive Descriptor Structure requires two words (8 bytes) of memory. Likewise
each Receive Status Structure requires two words (8 bytes) of memory. Receive
Descriptor Structures consist of a Packet word containing a pointer to a data buffer for
storing receive data and a Control word. The address offset of the Packet word in the
receive descriptor structure is 0, and the address offset of the Control word is offset
by 4 bytes with respect to the Receive Descriptor Structure address, as defined in
Table
Table 4: Receive Descriptor Structure
The Packet word is a 32-bit byte-aligned address value containing the base address
of the data buffer. The definition of the Control word bits are given in
Table 5: Receive Descriptor Control Word
Name
Packet
Control
Bit
31
30:11
10:0
4.
Name
Interrupt If set, generate an RxDone interrupt when the data in this packet or packet
Size
Address
Offset
0x0
0x4
Function
fragment and the associated status information has been committed to
memory.
Unused
Size in bytes of the data buffer. This is the size of the buffer reserved by
the device driver for a packet or packet fragment, i.e., the byte size of the
buffer pointed to by the Packet word. The size is –1 encoded, e.g., if the
buffer is 8 bytes, the size field should be equal to 7.
Rev. 2 — 1 December 2004
Size Function
31:0
31:0
Chapter 23: LAN100 — Ethernet Media Access Controller
Base address of the data buffer for storing receive data.
Control information, see
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Table
5.
PNX15xx Series
Table
5.
23-28