PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 666

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
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Product data sheet
2.3 Description
The Receive Datapath includes:
The Ethernet Media Access Controller (LAN100) and associated device driver
software offer the functionality of the Media Access Control (MAC) sublayer of the
data link layer in the OSI reference model (see IEEE Standard 802.3 [1]).
The MAC sublayer transmits and receives frames to and from the next higher protocol
level, the MAC client layer, typically the Logical Link Control sublayer. The device
driver software implements the interface to the MAC client layer. It sets up MMIO
registers in the LAN100, maintains FIFOs of packets in memory, and receives results
back from the LAN100, typically via interrupts.
When packets are transmitted, packet fields can be concatenated using the
scatter/gather DMA functionality of the LAN100 to avoid unnecessary data copying.
The hardware can add the preamble and start frame delimiter fields, and can
optionally add the CRC under program control. Or, software can partially set up the
Ethernet frames by concatenating the destination address field, source address field,
the length/type field, the MAC client data field, and optionally, the CRC in the frame
check sequence field of the Ethernet frame.
When a packet is received, the LAN100 strips the preamble and start frame delimiter
and passes the rest of the packet - the rest is the Ethernet frame - to the device
driver, including destination address, source address, length/type field, MAC client
data, and frame check sequence.
Apart from its basic packet management functions, the LAN100 contains receive and
transmit DMA managers that control receive- and transmit-data streams. Frames are
passed via descriptor FIFOs (arrays) located in host memory, so that the hardware
can process many packets without software or CPU support. Packets can consist of
multiple fragments that are accessed with scatter/gather DMA. The DMA managers
optimize memory bandwidth by prefetching and buffering.
The LAN100 is connected to the MTL bus using multiple DMA interfaces that perform
data buffering to adapt the data burst rate of the MTL bus to the data rate required for
the Ethernet protocol.
The LAN100 provides MMIO registers via a slave interface to the DCS bus to allow
software to access the internal registers of the LAN100.
Real-time traffic is supported using two transmit queues:
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Receive parser, which detects packet types by parsing part of the packet header
Receive filter, which can filter out certain Ethernet packets, applying different
filtering schemes
Receive buffer, which implements a delay for receive packets to allow the filter to
filter out certain packets before storing them to memory
Receive DMA manager, which reads descriptors from memory and writes data
and status to memory.
A real-time queue sends frames at the time specified in transmit time-stamps
Rev. 2 — 1 December 2004
Chapter 23: LAN100 — Ethernet Media Access Controller
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
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