PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 57

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 25: DDR DRAM Interface Timing
Table 26: PCI Bus Timing
12NC 9397 750 14321
Product data sheet
Symbol
T
T
T
Symbol
T
T
T
T
T
T
T
T
T
on-PCI
rst-off-PCI
Off-PCI
iskew-dqs
is-dq
ih-dq
clock
val-PCI (Bus)
val-PCI (ptp)
su-PCI
su-PCI (ptp)
h-PCI
Parameter
Maximum input skew supported
(when reading from DDR SDRAM)
Input setup time for MM_DQ
(when reading from DDR SDRAM)
Input hold time for MM_DQ
(when reading from DDR SDRAM)
Parameter
Minimum High and Low times
Clk to signal valid delay, bus signals
Clk to signal valid delay, point-to-point signals
Float to active delay
Active to float delay
Input setup time to CLK - bus signals
Input setup time to CLK - point-to-point signals
Input hold time from CLK
Reset active to output float delay
8.3 PCI Bus Interface
[25-1]
[25-2]
[25-3]
[25-4]
[25-5]
[25-6]
[26-1]
[26-2]
[26-3]
[26-4]
[26-5]
[26-6]
Notes:
1. Command signals include MM_CKE_N[1:0], MM_CS[1:0]_N, MM_RAS_N, MM_CAS_N,
MM_WE_N, MM_BA[1:0] and MM_A[13:0] signals.
2. Times are measured w.r.t. the positive edge of MM_CLK and the crossing point of
MM_CLK and MM_CLK_N.
3. Refer to
4. Times are measured w.r.t. the corresponding edge of MM_DQS[3:0], i.e. MM_DQS[0] if
the DDR device is organized in x32, or respectively MM_DQ[31:24], MM_DQ[23:16],
MM_DQ[15:8] and MM_DQ[7:0] (when applicable) if the DDR devices organized in x8 or x16
are used.
5. These timings allow a 250 ps maximum board level skew for MM_CK. MM_CK_N,
MM_DQS[3:0] and MM_DQ[31:0] for a 200 MHz operating frequency (i.e. DDR400).
Notes:
1. See the timing measurement conditions in
2. Minimum times are measured at the package pin with the load circuit shown in
Maximum times are measured with the load circuits shown in
3. PCI_REQ_N and PCI_GNT_N are point-to-point signals and have different input setup
times. All other signals are bused.
4. See the timing measurement conditions in
5. All output drivers are floated when PCI_RST (may be connected to RESET_IN_N and/or
POR_IN_N) is active.
Figure 2 on page 1-24
Rev. 2 — 1 December 2004
for load conditions.
Min
0.2
- 0.6
1.5
Min
11
2
2
2
7
12
Figure
Figure
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 1: Integrated Circuit Data
10.
10.
Max
1.8
Max
11
12
28
40
Figure
PNX15xx Series
Units
ns
ns
ns
11.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
Notes
2, 5
4, 5
4, 5
Notes
1
1,2,3
1,2,3
1
1,7
3,4
3,4
4
5,6
8.
1-31