PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 7
PNX1501E
Manufacturer Part Number
PNX1501E
Description
Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1501E.pdf
(819 pages)
Specifications of PNX1501E
Product
DSPs
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOT-795
Minimum Operating Temperature
0 C
Lead Free Status / Rohs Status
Details
Other names
PNX1501E,557
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Manufacturer:
PHILIPS
Quantity:
5
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Part Number:
PNX1501E,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Part Number:
PNX1501E/G
Manufacturer:
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Quantity:
135
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Part Number:
PNX1501E/G
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
PNX1501E/G
Manufacturer:
NXP/恩智浦
Quantity:
20 000
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Philips Semiconductors
Volume 1 of 1
Chapter 14: FGPI: Fast General Purpose Interface
1.
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.5
1.6
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
Chapter 15: Audio Output
1.
1.1
2.
2.1
2.2
2.2.1
2.3
2.3.1
2.4
2.4.1
2.5
2.6
2.6.1
2.6.2
Chapter 16: Audio Input
1.
1.1
2.
2.1
2.2
3.
3.1
3.1.1
3.2
3.3
12NC 9397 750 14321
Product data sheet
Introduction
Functional Description
Introduction
Functional Description
Introduction
Functional Description
Operation
FGPI Overview
VDI to FGPI pin mapping
DTL MMIO Interface
Data Packer
8-Bit Sample Packing Mode
16-bit Sample Packing Mode
32-bit Sample Mode
Record Capture Mode
Message Passing Mode
Reset
Base Addresses
Sample (data) Size
Record or Message Size
Records or Messages Per Buffer
Stride
Interrupt Events
BUF1FULL and BUF2FULL Interrupts
THRESH1_REACHED and
THRESH2_REACHED Interrupts
OVERRUN Interrupt
MBE Interrupt
OVERFLOW Interrupt (Message Passing Mode
Only)
Features
External Interface
Memory Data Formats
Endian Control
Audio Out Data DMA Operation
TRANS_ENABLE
Interrupts
Interrupt Latency
Timestamp Events
Serial Data Framing
Serial Frame Limitations
WS Characteristics
Features
Chip Level External Interface
General Operations
Clock Programming
Clock System Operation
Reset-Related Issues
Register Programming Guidelines
14-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
. . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
. . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
. . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
. . . . . . . . . . . . . . . . . . . . . . . . . 14-7
. . . . . . . . . . . . . . . . . . . . . . . . . 15-6
. . . . . . . . . . . . . . . . . . . . . . . . 15-2
. . . . . . . . . . . . . . . . . . . . . . . . 15-5
. . . . . . . . . . . . . . . . . . . . . . . 14-7
. . . . . . . . . . . . . . . . . . . . . . . 15-6
. . . . . . . . . . . . . . . . . . . . . . . 15-8
. . . . . . . . . . . . . . . . . . . . . . 14-4
. . . . . . . . . . . . . . . . . . . . . . 14-8
. . . . . . . . . . . . . . . . . . . . . . 15-6
. . . . . . . . . . . . . . . . . . . . . . 16-4
. . . . . . . . . . . . . . . . . . . . . . 16-5
. . . . . . . . . . . . . . . . . . . . . 14-3
. . . . . . . . . . . . . . . . . . . . 14-4
. . . . . . . . . . . . . . . . . . . . 15-4
. . . . . . . . . . . . . . . . . . . . 16-6
. . . . . . . . . . . . . . . . . . 14-4
. . . . . . . . . . . . . . . . . . 14-7
. . . . . . . . . . . . . . . . . . 15-8
. . . . . . . . . . . . . . . . . . 16-5
. . . . . . . . . . . . . . . . . 14-3
. . . . . . . . . . . . . . . . . 14-6
. . . . . . . . . . . . . . . . . 15-1
. . . . . . . . . . . . . . . . . 16-2
. . . . . . . . . . . . . . . 14-4
. . . . . . . . . . . . . . 14-4
. . . . . . . . . . . . . . 16-3
. . . . . . . . . . . 15-5
14-8
. . . . . . . . . . 14-8
. . . . . . . . . 16-7
. . . . . . 14-8
Rev. 2 — 1 December 2004
2.8
2.9
2.10
2.11
2.12
2.13
3.
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2
3.2.1
3.3
3.4
3.4.1
3.4.2
3.4.3
4.
4.1
4.2
2.6.3
2.7
2.8
2.9
3.
3.1
3.1.1
3.1.2
3.2
3.3
3.4
4.
4.1
4.2
3.4
3.5
3.5.1
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
Operation
Register Descriptions
Operation
Register Descriptions
Record or Message Counters
Timestamp
Variable Length
Double Buffer Operation
Single Buffer Operation
Buffer Synchronization
Both Operating Modes
Setup
Interrupt Service Routines
Optimized DMA Transfers
Terminating DMA Transfers
Signal Edge Definitions
Message Passing Mode
Minimum Message/Record Size
PNX1300 Series Message Passing Mode
Record Capture Mode
Record Synchronization
Buffer Synchronization
Setup and Operation with Input Router
VDI_MODE[7] = 1
Mode Registers
Status Registers
I
Codec Control
Data Bus Latency and HBE
Error Behavior
Clock Programming
Sample Clock Generator
Clock System Operation
Reset-Related Issues
Register Programming Guidelines
Power Management
Register Summary
Register Table
Serial Data Framing
Memory Data Formats
Endian Control
Memory Buffers and Capture
Data Bus Latency and HBE
Error Behavior
Interrupts
Timestamp Events
Diagnostic Mode
Software Reset
Raw Mode
2
S Serial Framing Example
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
PNX15xx Series
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
. . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
. . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
. . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
. . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
. . . . . . . . . . . . . . . . . . . . . . . . . . 16-12
. . . . . . . . . . . . . . . . . . . . . . . . . 14-10
. . . . . . . . . . . . . . . . . . . . . . . . . 14-18
. . . . . . . . . . . . . . . . . . . . . . . . . 16-14
. . . . . . . . . . . . . . . . . . . . . . . . 14-21
. . . . . . . . . . . . . . . . . . . . . . . . 16-13
14-16
. . . . . . . . . . . . . . . . . . . . . . 15-15
. . . . . . . . . . . . . . . . . . . . . . 16-13
. . . . . . . . . . . . . . . . . . . . . 15-12
. . . . . . . . . . . . . . . . . . . . . 15-14
. . . . . . . . . . . . . . . . . . . . . . 16-7
. . . . . . . . . . . . . . . . . . . . 15-14
. . . . . . . . . . . . . . . . . . . 14-12
. . . . . . . . . . . . . . . . . . . 14-12
. . . . . . . . . . . . . . . . . . . 14-15
. . . . . . . . . . . . . . . . . . . 14-15
. . . . . . . . . . . . . . . . . . . 16-10
. . . . . . . . . . . . . . . . . . 14-11
. . . . . . . . . . . . . . . . . . 14-13
. . . . . . . . . . . . . . . . . . 14-14
. . . . . . . . . . . . . . . . . . 14-15
. . . . . . . . . . . . . . . . . . 14-18
. . . . . . . . . . . . . . . . . . 15-15
. . . . . . . . . . . . . . . . . 14-10
. . . . . . . . . . . . . . . . . 15-12
. . . . . . . . . . . . . . . . . 15-13
. . . . . . . . . . . . . . . . 14-13
. . . . . . . . . . . . . . . . 14-13
. . . . . . . . . . . . . . . 15-10
. . . . . . . . . . . . . . . 16-11
. . . . . . . . . . . . . . 14-13
. . . . . . . . . . . . . . . 15-8
. . . . . . . . . . . . . . 14-9
. . . . . . . . . . . . . 16-11
. . . . . . . . . . . 14-14
. . . . . . . . . 15-14
. . 14-15
-7
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