PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 492

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
3.4.3 Setup and Operation with Input Router VDI_MODE[7] = 1
(see
The buffer start event switches to a new buffer as soon as a concurrent or following
record start event is detected IF double buffering is enabled.
For rising, falling, and alternate buffer start events the programmed number of
records (FGPI_SIZE) for the current buffer may be reached before the next buffer
start event. If this happens the capture of data is stopped until the next buffer and
record start events. If a record start event occurs before the buffer start event, it will
be ignored. A buffer start event may occur before the next record start event.
For rising, falling, and alternate buffer start events the current buffer may also be
terminated by receiving a buffer start event before the programmed number of
records (FGPI_SIZE) is reached. If record start event is rising or falling then the
current record will finish being loaded into the current buffer before switching to the
next buffer. If record start event is ignored the current buffer is only partially filled and
the content of the remaining buffer is undefined. Subsequent samples will be stored
in the next buffer.
When no buffer sync is used the fgpi_stop (fgpi_buf_start) pin is ignored. In this mode
each buffer will contain FGPI_SIZE records and buffer switching occurs immediately
after a buffer fills.
When no buffer or record sync is used data samples are sampled and stored
continuously. This mode is called “free running” or “raw capture”.
See the Global Register specification for more information. Setting the VDI_MODE bit
7 activates an fgpi_data stream pre-processor that extracts the SAV/EAV sync
signals (as defined in the video CCIR 656 standard) out of an 8-bit D1 stream and
generates the fgpi_start (fgpi_rec_start) and fgpi_stop (fgpi_buf_start) control
signals.
FGPI and Input Router Setup Requirements:
•
•
•
•
•
a rising edge on fgpi_stop (fgpi_buf_start) pin
a falling edge on fgpi_stop (fgpi_buf_start) pin
alternating rising & falling edges on fgpi_stop (fgpi_buf_start) pin, starting with a
rising edge
alternating rising & falling edges on fgpi_stop (fgpi_buf_start) pin, starting with a
falling edge
occur immediately after the previous buffer is filled or when capture is started
–
–
–
–
Section 3.1.5 on page 14-13
The 8-bit data stream must be applied to the fgpi_data[7:0] pins
VDI_MODE[7] = 1, VDI_MODE[4:3] = xx (don’t care), VDI_MODE[1:0] = 01
FGPI_CTL_MODE = 0 (Record Mode)
FGPI_CTL_SAMPLE_SIZE = 00 (8-bit samples packed 4 samples per 32-bit
word)
Rev. 2 — 1 December 2004
Chapter 14: FGPI: Fast General Purpose Interface
for signal definitions for rising and falling edges).
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
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