PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 551

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
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Product data sheet
Figure 1:
SPDI_IN
SPDIF Input Block Diagram
pin
2.2.1 Functional Modes
2.2 Architecture
Oversampling clock
domain
SPDIF
Input
storage in main memory using a hardware double buffered scheme. In addition,
during the decode phase, the input stream is processed to extract parity, validity and
selected channel status information for each IEC60958 block.
The SPDIF bitstream is composed of a single signal that is organized into a block
structure of 192 frames. The signal has both data and an embedded clock present.
Each frame is composed of 2 subframes each composed of 32 bits. The stream is
encoded with a line code called “bi-phase mark” encoding.
organization of the IEC60958 SPDIF stream format.
The input stream is parsed by the hardware using an extracted bitclock that is
synchronous to the oversampling clock. The audio data, validity flag, channel status
and parity bits are extracted and the SPDI_STATUS and SPDI_CBITS registers are
updated, see
are up to 24 bits in length.
The SPDIF Input module has 3 major functional modes. All modes are configured via
software programmable MMIO registers, see
32-bit Mode: Subframe bits [27:4] inclusive are selected and stored subject to a
programmable bitmask. A 32-bit word is formed by padding ‘0’ bits to the least
significant end of the masked audio samples. In addition, the state of the parity bit
and the validity bit of each subframe is sampled and the SPDI_STATUS register is
updated with the results. This mode provides for any audio sample size ranging from
17 to 24 bits.
•
16-bit Mode: Subframe bits [27:12] inclusive are selected and stored. All biphase
encoded bits are decoded. In addition, the state of the parity bit and the validity
bit of each subframe is sampled and the SPDI_STATUS register is updated with
the results. This mode is useful when the stream contains either 16-bit PCM
audio or 16-bit non-PCM samples.
dtl_mmio_clk
domain
SPDIF
Input
Figure
Rev. 2 — 1 December 2004
9. The audio portion of each subframe can contain samples that
Control
Registers
DMA UNIT
DATA
32
Figure
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
9. These modes are:
PNX15xx Series
MTL Bus
to External memory
Chapter 18: SPDIF Input
Figure 2
Memory
clock domain
shows the
18-2