PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 59

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 27: QVCP, LCD and FGPO Timing With Internal Clock Generation
Table 28: QVCP, LCD and FGPO Timing With External Clock Generation
12NC 9397 750 14321
Product data sheet
Symbol
F
F
T
T
T
Symbol
F
F
T
T
T
QVCP
FGPO
CLK-DV
SU-CLK
H-CLK
QVCP
FGPO
CLK-DV
SU-CLK
H-CLK
Parameter
VDO_CLK1 frequency
VDO_CLK2 frequency
Clock to VDO_D[33:0] and VDO_AUX
Input setup time
Input hold time
Parameter
VDO_CLK1 frequency
VDO_CLK2 frequency
Clock to VDO_D[33:0] and VDO_AUX
Input setup time
Input hold time
8.4 QVCP, LCD and FGPO Interfaces
[27-1]
[27-2]
[27-3]
[27-4]
[27-5]
[28-1]
[28-2]
[28-3]
Figure 12: QVCP and FGPO I/O Timing
See timing measurement conditions
Timing applies when the data is output on a positive or a negative edge in double edge clock
mode, see
If the VDO_CLK[1,2] is inverted internally then the timing applies to the negative edge.
Timing applies for VDO_D[29], FGPO_REC_SYNC and FGPO_BUF_SYNC. VDO_D[29]
and FGPO_BUF_SYNC. This inputs are assumed asynchronous.
In double edge clock mode, the maximum VDO_CLK1 frequency is 65 MHz. In single edge
clock mode, positive or negative edge, the maximum VDO_CLK1 is 81 MHz.
See timing measurement conditions
Timing applies when the data is output on a positive or a negative edge in double edge clock
mode, see
3. If the VDO_CLK[1,2] is inverted internally then the timing applies to the negative edge.
Table 1 on page
Table 1 on page
Rev. 2 — 1 December 2004
FGPO_REC_SYNC
FGPO_BUF_SYNC
FGPO_REC_SYNC
FGPO_BUF_SYNC
VDO_D[34:0]
VDO_D[29]
VDO_CLK
VDO_CLK
3-6.
3-6.
Figure
Figure
Min
1.5
3
2
Min
3
4
4
12.
12.
T
SU-CLK
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 1: Integrated Circuit Data
Max
65-81
100
6
Max
81
81
11
valid
PNX15xx Series
T
T
CLK-DV
H-CLK
valid
Units
MHz
MHz
ns
ns
ns
Units
MHz
MHz
ns
ns
ns
Notes
5
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
Notes
5
5
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1-33