PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 570

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 6: SPDIF Input Registers
12NC 9397 750 14321
Product data sheet
Bit
7
6
5
4
3
2
1
0
Offset 0x10 AFE4
31:10
9
8
7
6
Symbol
LOCK
VERR
PERR
OVERRUN
HBE (Bandwidth error)
BUF1_ACTIVE
BUF2_FULL
BUF1_FULL
Unused
UNLOCK_ENBL
UCBITS_ENBL
LOCK_ENBL
VERR_ENBL
SPDI_INTEN
…Continued
Acces
s
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
Value
0
0
0
0
0
0
0
0
-
0
0
0
0
Rev. 2 — 1 December 2004
Description
LOCK active
1 = The SPDIF Input receiver achieved lock onto the incoming
stream. Use this LOCK flag, in conjunction with the UNLOCK flag,
to determine the state of the receiver or to make a decision to adjust
the oversampling frequency. The flag can be cleared by a software
write to LOCK_CLR. LOCK means that the internal PLL is locked. A
valid sequence of preambles is not required for LOCK.
Validity Error
1 = The hardware encounters a subframe that has the validity flag
set to 1, indicating that the payload portion of the subframe is not
reliable. The flag can be cleared by a software write to VERR_CLR.
Parity Error
1 = The hardware encounters a subframe that has a parity error.
Parity is even for the subframe and applies to subframe bits [31:4]
inclusive. Normally, the external SPDIF Input transmitter will set the
subframe P bit to logic ‘1’ or logic ‘0’ so that bits [31:4] have an even
number of logic “1s” and “0s”. The flag can be cleared by a software
write to PERR_CLR.
1 = Both external main memory DMA buffers are filled before a new
empty buffer is assigned by the system control CPU. Hardware has
performed a normal buffer switch over and is overwriting fresh,
unconsumed data. This flag can be cleared by software write to
OVR_CLR.
Bandwidth Error
1 = The internal hardware DMA buffers in SPDI are full and at least
one of them was not emptied before new input data arrived on the
SPDI interface, indicating that DMA service latency is too long. This
flag can be cleared by a software write to HBE_CLR.
This flag is set to logic ‘1’ if the hardware is currently filling memory
DMA buffer 1. Otherwise, it is reset to logic ‘0’. This flag can be
cleared by a software write to BUF1_ACTIVE_CLR.
This flag is set to logic ‘1’ if memory DMA buffer 2 has been filled by
the SPDI hardware. It can be cleared by a software write to
BUF2_FULL_CLR.
This flag is set to logic ‘1’ if memory DMA buffer 1 has been filled by
the SPDI hardware. It can be cleared by a software write to
BUF1_FULL_CLR.
1 = UNLOCK bit in SPDI_STATUS is enabled for interrupts.
0 = UNLOCK bit in SPDI_STATUS is disabled for interrupts.
1 = UCBITS bit in SPDI_STATUS is enabled for interrupts.
0 = UCBITS bit in SPDI_STATUS is disabled for interrupts.
1 = LOCK bit in SPDI_STATUS is enabled for interrupts.
0 = LOCK bit in SPDI_STATUS is disabled for interrupts.
1 = VERR bit in SPDI_STATUS is enabled for interrupts.
0 = VERR bit in SPDI_STATUS is disabled for interrupts.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
Chapter 18: SPDIF Input
18-21