PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 164

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
2.11.1 Setting GPIO[14:12]/GCLOCK[2:0] as Clock Outputs
2.11.2 GPIO[6:4]/CLOCK[6:4] as Clock Outputs
2.11 GPIO Clocks
2.12 Clock Block Diagrams
protecting an input clock from contention by having the pad set to an input (in the
case of an input clock). In both cases a write to each control register is necessary to
properly put the clock into an input or output configuration (otherwise the logic will
remain in the quasi-input/output mode).
As indicated above VDO_CLK1 can either be QVCP or LCD. After reset the clocks
are in the above mentioned quasi-input/output mode. If it is to be LCD then the
qvcp_out control register must be programmed to “separate” output mode. If the LCD
only bit (bit 31 in the LCD_SETUP MMIO register) is set then the output select bit in
the qvcp_out control register cannot be written to a ‘1’ (feedback mode). The LCD
mode register can only be written to once and then only to disable LCD mode. If this
is done then the output select bit can be programmed to any value.
The folowing sections present the sequence of actions required to enable clocks on
the GPIO[12:14,6:4’ pins.
The following sections present the block diagrams of the different clocks generated by
the Clock module.
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Set gpio pin to gpio mode 2 using GPIO_MODE_0_15
Set gpio pin to output a 0 using GPIO_MASK_IOD_0_15
Set dds frequency using DDSx_CTL
Enable dds output to clk_gpio_y using CLK_GPIO_y_CTL
page
Enable clk_gpio_y to pin using DDS_OUT_SEL
Set gpio pin to gpio mode 2 using GPIO_MODE_0_15
Set gpio pin to output a 0 using GPIO_MASK_IOD_0_15
Set dds frequency using DDSx_CTL
Enable dds output to clk_gpio_y using CLK_GPIO_y_CTL
page
Set GPIO_EV_x.EN_DDS_SOURCE = 1 and GPIO_EV_x.CLOCK_SEL = 4 for
GPIO[4], 5 for GPIO[5] and 6 for GPIO[6]
5-34)
5-34)GPIO_EV_x.
Rev. 2 — 1 December 2004
(Table 11 on page
(Table 11 on page
(Table 10 on page
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
(Table 16 on page
Chapter 5: The Clock Module
PNX15xx Series
(Table 7 on page
(Table 7 on page
5-34)
5-34)
(Table 8 on page
(Table 8 on page
(Table 11 on
(Table 11 on
8-27)
8-36)
8-24)
8-24)
8-26)
8-26)
5-20