mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 122

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Instruction Cache Overview
4-16
14–13
12–7
Bits
4–3
1–0
6
5
2
Name
BWE
CM
WP
SM
—
—
—
Supervisor mode. Specifies whether only user or supervisor accesses are allowed in this address
range or if the type of access is a don’t care.
00 Match addresses only in user mode
01 Match addresses only in supervisor mode
1x Execute cache matching on all accesses
Reserved; should be cleared.
Cache mode. Defines whether the memory access is cacheable or noncacheable.
0 Caching enabled
1 Caching disabled
Buffered write enable. Generally, the enabling of buffered writes provides higher system
performance but recovery from access errors may be more difficult. For the ColdFire CPU, reporting
access errors on operand writes is always imprecise; enabling buffered writes further decouples the
write instruction from the signaling of the fault.
0 Termination of an operand write cycle on the processor's local bus is delayed until the external
1 A write cycle on the local bus is terminated immediately and the operation is then buffered in the
Reserved, should be cleared.
Write protect. Selects the write privilege of the memory region.
0 Read and write accesses permitted
1 Write accesses not permitted
Reserved, should be cleared.
bus cycle is completed.
bus controller. In this mode, operand write cycles are effectively decoupled between the
processor's local bus and the external bus.
Table 4-9. ACRn Field Descriptions (Continued)
MCF5272 User’s Manual
Description
MOTOROLA