mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 204

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Performance
In self-refresh mode, SDRAM devices can refresh themselves without an external clock.
After power-down completes, SDCR[SLEEP] is set, the SDRAM clock output is driven
high, and SDCLKE is driven low.
To wake up the SDRAMs, SDCR[GSL] must be cleared. SDCR[SLEEP] remains set while
the SDRAM is exiting sleep mode and is cleared when the SDRAM completes the correct
sequence to exit sleep mode.
9.8 Performance
The maximum performance of the SDRAM controller is determined by the required
number of cycles for page activation and precharge. The read access is influenced by the
CAS latency. All SDRAM accesses are in page mode. The following table shows the
number of required cycles including all dead cycles for each type of read/write SDRAM
access. It assumes default timing configuration using an at least PC100-compliant SDRAM
device at 66 MHz. Page miss latency includes the cycles to precharge the last open page
and activate the new page before the read/write access. There are no precharge cycles when
an address hits an open page.
In Table 9-9, the timing configuration is RTP = 61, RC = negligible, RCD = 0 (or 1), RP = 1
(or 0), and CLT = 1.
In Table 9-10, the timing configuration is RTP = 61, RC = negligible, RCD = 0, RP = 0, and
CLT = 1.
9-10
Table 9-9. SDRAM Controller Performance, 32-Bit Port, (RCD = 0, RP = 1) or
Single-beat read
Single-beat write
Burst read
Burst write
SDRAM Access
Page miss
Page hit
Page miss
Page hit
Page miss
Page hit
Page miss
Page hit
MCF5272 User’s Manual
(RCD = 1, RP = 0)
8
5
6
3
8-1-1-1 = 11
5-1-1-1 = 8
6-1-1-1 = 9
3-1-1-1 = 6
REG = 0, INV = 0
Number of System Clock Cycles
9
6
6
3
9-1-1-1 = 12
6-1-1-1 = 9
6-1-1-1 = 9
3-1-1-1 = 6
REG = 1, INV = 0
MOTOROLA