mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 283

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
12.3.2.16 USB Endpoints 1–7 Status / Interrupt Registers (EPnISR)
Figure 12-19 shows the USB endpoints 1-7 status/interrupt registers.
Table 12-15 lists field descriptions for the USB endpoints 1–7 interrupt status registers.
Bits
3
2
1
0
12–5
Bits
Reset
15
14
13
Field HALT_ST DIR PRES
Addr
R/W
Figure 12-19. USB Endpoints 1–7 Interrupt Status Registers (EP
Table 12-14. EP0IMR and EP0ISR Field Descriptions (Continued)
UNHALT
IN_EOP
IN_LVL
Name
HALT_ST Current status of endpoint n. This bit indicates whether endpoint n is currently halted or
HALT
Interrupt bits are cleared by writing a 1 to the specified bits. Bits 13–15 are read-only status bits.
15
Name
PRES
DIR
—
14
active. HALT_ST is set due to a SET_FEATURE request with the endpoint halt feature
selector set or a STALL response to an IN or OUT packet. HALT_ST is cleared by a
CLEAR_FEATURE request with the endpoint halt feature selector set.
0 Endpoint n active
1 Endpoint n halted
Current direction of endpoint n. This bit indicates whether endpoint n is currently
configured as an IN or OUT endpoint.
0 Endpoint n configured as an OUT endpoint
1 Endpoint n configured as an IN endpoint
Endpoint n present. This bit indicates whether or not endpoint n is present in the current
configuration.
0 Endpoint n absent
1 Endpoint n present
Reserved, should be cleared.
End of packet. This bit is set when a packet has been sent successfully for endpoint 0 IN.
0 No interrupt pending
1 IN packet sent successfully
Unhalt. This bit is set when the endpoint 0 HALT_ST bit is cleared by a SETUP packet or
USB reset.
0 No interrupt pending
1 Endpoint halt cleared
Halt. This bit is set when the endpoint 0 HALT_ST bit is set due to a STALL response to
the host.
0 No interrupt pending
1 Endpoint halted
IN FIFO threshold level. This bit indicates that the FIFO level has fallen below the level
set in the EPCTL0 register.
0 No interrupt pending
1 IN FIFO threshold level reached
MBAR + 0x1072, 0x1076, 0x107A, 0x107E, 0x1082, 0x1086, 0x108A
Table 12-15. EP
13
Chapter 12. Universal Serial Bus (USB)
12
0000_0000_0000_0000
n
—
ISR Field Descriptions
Register Description and Programming Model
Description
Description
5
EOT EOP UNHALT HALT FIFO_LVL
4
3
2
n
1
ISR)
0
12-23