mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 229

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

FEC Frame Transmission
transmit, DMA of the transmit data buffer(s) begins immediately. A collision window (512
bits) of transmit data is sent as a DMA to the transmit FIFO before off-chip transmission
begins.
When the transmit FIFO contains 512 bits of data, the FEC asserts E_TxEN and starts
transmitting the preamble sequence, the start-of-frame delimiter, and then the frame data.
However, if the line is busy, the controller defers the transmission (carrier sense is active).
Before transmitting, the controller waits for carrier sense to become inactive. When carrier
sense goes inactive, the controller waits to verify that it stays inactive for 60 bit times. If so,
the transmission begins after waiting an additional 36 bit times (96 bit times after carrier
sense originally went inactive).
If a collision occurs during the transmit frame, the FEC follows the specified backoff
procedures and attempts to retransmit the frame until the retry limit is reached. The FEC
stores the first 64 bytes of the transmit frame in internal RAM, so they need not be retrieved
from system memory in case of a collision. This improves external bus use and reduces
latency whenever the backoff process results in an immediate retransmission.
See Figure 11-27 on page 11-34 for the following discussion. When the end of the last
transmit buffer in the current frame is reached, the 32-bit frame check sum is appended (if
TxBD[TC] is set) and transmission is disabled (E_TxEN is negated). Following the
transmission of the check sum, the FEC writes the frame status bits into the buffer
descriptor and clears the ready bit. When the end of the current BD is reached but it is not
the last buffer in the frame, then only the ready bit is cleared. Short frames are automatically
padded by the transmit logic.
If the transmit frame length exceeds the value programmed in the maximum frame length
register, the BABT interrupt is asserted. However, the entire frame is transmitted and is not
truncated. See Section 11.5.14, “Maximum Frame Length Register (MFLR).”
Both buffer and frame interrupts may be generated as determined by the EIMR register
settings.
Setting the graceful transmit stop bit, TCR[GTS], pauses transmission. The FEC
transmitter stops immediately if no transmission is in progress. Otherwise it continues
transmission until the current frame finishes normally or terminates with a collision. When
TCR[GTS] is cleared, the FEC resumes transmission with the next frame.
The FEC transmits bytes lsb first.
11.4.1 FEC Frame Reception
The FEC receiver is designed to work with almost no intervention from the host and can
perform address recognition, CRC, short frame checking, and maximum frame length
checking.
MOTOROLA
Chapter 11. Ethernet Module
11-5