mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 455

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Chapter 20
Bus Operation
The MCF5272 bus interface supports synchronous data transfers that can be terminated
synchronously or asynchronously and also can be burst or burst-inhibited between the
MCF5272 and other devices in the system. This chapter describes the functioning of the bus
for data-transfer operations, error conditions, bus arbitration, and reset operations. It
includes detailed timing diagrams showing signal interaction. Refer also to Figure 19-1 for
an overview of how the signals interact with each module of the MCF5272.
Operation of the bus is defined for transfers initiated by the MCF5272 as a bus master. The
MCF5272 does not support external bus masters. The MCF5272 has three on-chip bus
masters—the CPU, the Ethernet controller, and the memory-to-memory DMA controller.
20.1 Features
The following list summarizes the key bus operation features:
20.2 Bus and Control Signals
Table 20-1 summarizes MCF5272 bus signals described in Chapter 19, “Signal
Descriptions.”
• 23 bits of address and 32 bits of data
• Device physical data bus width configurable for 16 or 32 bits
• Accesses 8-, 16-, and 32-bit port sizes
• Generates byte, word, longword, and line size transfers
• Burst and burst-inhibited transfer support
• Internal termination generation
Table 20-1. ColdFire Bus Signal Summary
Signal Name
BS[3:0]
CS[7:0]
A[22:0]
D[31:0]
Chapter 20. Bus Operation
Address bus
Byte strobes
Chip selects
Data bus
Description
I/O
I/O
O
O
O
20-1