mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 318

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

P0PSR–3
PLIC Registers
13.5.10 Periodic Status Registers (P0PSR–P3PSR)
All bits in these registers are read only and are set on hardware or software reset.
13-22
Bits
7–6
Reset
10
9
8
5
4
3
2
1
0
Addr
R/W
15
B2RIE
B1RIE
Name
B2TIE
B1TIE
DRIE
GMR
GMT
DTIE
—
GCT
—
12
Table 13-4. P0ICR–P3ICR Field Descriptions (Continued)
Figure 13-22. Periodic Status Registers (P0PSR–P3PSR)
DTUE B2TUE B1TUE DROE B2ROE B1ROE DTDE B2TDE B1TDE DRDF B2RDE B1RDF
11
C/I channel transmit Interrupt enable.
0 Interrupt masked
1 Interrupt enabled.
Interrupt enable for the monitor channel receive.
0 Interrupt masked
1 Interrupt enabled.
Interrupt enable for the monitor channel transmit.
0 Interrupt masked
1 Interrupt enabled.
Reserved, should be cleared.
D transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled.Interrupt occurs when the corresponding PnPSR[DTDE] or PnPSR[DTUE]
B2 transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B2TDE] or
B1 transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B1TDE] or
D receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[DRDF] or
B2 receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B2RDF] or
B1 receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled.Interrupt occurs when the corresponding PnPSR[B1RDF] or
PnPSR[B1ROE] is set.
is set.
PnPSR[B2TUE] is set.
PnPSR[B1TUE] is set.
PnPSR[DROE] is set.
PnPSR[B2ROE] is set.
MBAR + 0x384 (P0PSR); 0x386 (P1PSR); 0x388 (P2PSR); 0x38A (P3PSR)
10
9
MCF5272 User’s Manual
8
0000_0000_0000_0000
7
Read Only
Description
6
5
4
3
2
MOTOROLA
1
0