mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 185

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Table 7-4 describes ISR fields.
7.2.4 Programmable Interrupt Transition Register (PITR)
The programmable interrupt transition register (PITR), Figure 7-7, specifies the triggering
(either high-to-low or low-to-high) on each of the external interrupt inputs.
Table 7-5 describes PITR fields.
7.2.5 Programmable Interrupt Wakeup Register (PIWR)
The programmable interrupt wakeup register (PIWR), Figure 7-8, is used to specify which
interrupt sources are capable of causing the CPU to wake up from low-power SLEEP or
STOP modes when their source is active. All sources are disabled on reset. Note that only
the external interrupt pins INT[6:1] can wake up the CPU from STOP mode.
If more than one interrupt source has the same interrupt priority level (IPL) programmed in
the ICRs, the interrupt controller daisy chains the interrupts with the priority order
following the bit placement in the PIWR, with INT1 having the highest priority and SWTO
having the lowest priority as shown in Figure 7-8.
31–28,
31–4
27–7,
Bits
3–0
Bits
6, 5
4–0
Reset
Reset
Field INT1 INT2 INT3 INT4
Field
Addr
R/W
Field
31
15
Name
—
—
Figure 7-7. Programmable Interrupt Transition Register (PITR)
—
—
30
0 Interrupt source is high.
1 Interrupt source is low.
Reserved, should be cleared.
0 Triggering edge of external interrupt input is high-to-low (negative edge triggered).
1 Triggering edge of external interrupt input is low -to-high (positive edge triggered).
Reserved, should be cleared.
29
28
Table 7-5. PITR Field Descriptions
Table 7-4. ISR Field Descriptions
—
27
Chapter 7. Interrupt Controller
0000_0000_0000_0000
0000_0000_0000_0000
MBAR + 0x034
R/W
Description
Description
7
INT5
6
—
INT6
5
Interrupt Controller Registers
4
—
16
0
7-7