mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 139

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is
sampled on the rising edge of the processor CLK as well as the DSI. DSO is delayed from
the DSCLK-enabled CLK rising edge (registered after a BDM state machine state change).
All events in the debug module’s serial state machine are based on the processor clock
rising edge. DSCLK must also be sampled low (on a positive edge of CLK) between each
bit exchange. The MSB is transferred first. Because DSO changes state based on an
internally-recognized rising edge of DSCLK, DSDO cannot be used to indicate the start of
a serial transfer. The development system must count clock cycles in a given transfer.
C1–C4 are described as follows:
5.5.2.1 Receive Packet Format
The basic receive packet, Figure 5-13, consists of 16 data bits and 1 status bit.
Table 5-15 describes receive BDM packet fields.
16
S
• C1—First synchronization cycle for DSI (DSCLK is high).
• C2—Second synchronization cycle for DSI (DSCLK is high).
• C3—BDM state machine changes state depending upon DSI and whether the entire
• C4—DSO changes to next value.
BDM State
15
PSTCLK
input data transfer has been transmitted.
Machine
DSCLK
DSO
DSI
A not-ready response can be ignored except during a
memory-referencing cycle. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
Figure 5-12. BDM Serial Interface Timing
Current State
Figure 5-13. Receive BDM Packet
Past
Chapter 5. Debug Support
C1
Current
C2
NOTE:
Data Field [15:0]
C3
C4
Background Debug Mode (BDM)
Next State
Current
Next
5-17
0