mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 485

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
21.3 TAP Controller
The TAP controller is a synchronous state machine that controls JTAG logic and interprets
the sequence of logical values on TMS. The value adjacent to each arrow in the state
machine in Figure 21-2 reflects the value of TMS sampled on the rising edge of TCK. For
a description of the TAP controller states, refer to the IEEE 1149.1 document.
PSTCLK
MTMOD Motorola test mode select. Negating MTMOD enables JTAG mode; asserting it enables BDM mode.
TDI/DSI
DSCLK
Signal
TRST/
BKPT
TCK/
TMS/
TDO/
DSO
Test clock. TCK is the dedicated JTAG test logic clock input, independent of the CPU system clock. It
provides a clock for on-board test logic defined by the IEEE 1149.1 standard. TCK should be grounded if
the JTAG port is not used and MTMOD is tied low.
Test mode select. This input controls test mode operations for on-board test logic defined by the IEEE
1149.1 standard. Connecting TMS to VDD disables the test controller, making all JTAG circuits
transparent to the system.
Test and debug data out. Output for shifting data out of serial data port logic. Shifting out data depends on
the state of the JTAG controller state machine and the instructions in the instruction register. The shift
occurs on the falling edge of TCK. When not outputting data, TDO is placed in high-impedance state.
TDO can also be three-stated to allow bused or parallel connections to other devices having JTAG test
access ports.
Test and debug data in. Input provided for loading serial data port shift registers (boundary-scan, bypass,
and instruction registers). Shifting in of data depends on the state of the JTAG controller state machine
and the instruction currently in the instruction register. Data is shifted in on the rising edge of TCK.
JTAG test reset. TRST asynchronously resets the JTAG TAP logic when low.
Chapter 21. IEEE 1149.1 Test Access Port (JTAG)
Table 21-1. JTAG Signals
Description
TAP Controller
21-3