mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 514

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

1
2
3
4
P1
P4
P5
P6
Name
P10
P11
PLIC Module: IDL and GCI Interface Timing Specifications
23.9 PLIC Module: IDL and GCI Interface Timing
Table 23-17 shows timing for IDL master mode, PLIC ports 1, 2, and 3.
P2
P3
P7
P8
P9
For most telecommunications applications the period should be set to 125 µS. Refer to clock generator planning in
PLIC chapter.
Same as DCL0 and FSC0 if internal clock generator configured for pass-through mode.
GDCL1_OUT must be less than 1/20th of the CPU operating frequency. This is to ensure minimum jitter to CODECs
that may be connected to Ports 1,2,3.
Based on generated GDCL1_OUT less than 1/20 of CPU clock frequency.
23-20
1, 2
3, 2
4, 2
4, 2
DFSC[1:3] period
Delay from rising edge of GDCL1_OUT to rising edge of DFSC[3:1]
Delay from rising edge of GDCL1_OUT to DFSC[3:1] Invalid (output Hold
GDCL1_OUT clock period
GDCL1_OUT pulse width high
GDCL1_OUT pulse width low
Delay from rising edge of GDCL1_OUT to Low-Z and valid data on DOUT[1,3]
Delay from rising edge of GDCL1_OUT to DOUT[3:1] Invalid (Output Hold)
Delay from rising edge of GDCL1_OUT to High-Z on DOUT[1,3]
Data valid on DIN[1:3] before falling edge of GDCL1_OUT (setup time)
Data valid on DIN[1:3] after falling edge of GDCL1_OUT (hold time)
Specifications
Table 23-17. IDL Master Mode Timing, PLIC Ports 1, 2, and 3
Characteristic
Figure 23-16. UART Timing
URTn_CTS
URTn_RTS
URTn_RxD
URTn_TxD
SDCLK
MCF5272 User’s Manual
UT1
UT3
UT5
UT7
UT2
UT4
UT6
UT8
Min
20T
45
45
25
25
—
—
—
2
2
Typ
125
50
50
—
—
—
—
—
—
—
—
Max
20
—
—
55
55
30
—
30
—
—
MOTOROLA
% of period
% of period
Unit
µS
nS
nS
nS
nS
nS
nS
nS