mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 163

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
The initial references at address 0 and 4 are never captured nor displayed since these
accesses are treated as instruction fetches.
For all types of exception processing, the PST = 0xC value is driven at all times, unless the
PST output is needed for one of the optional marker values or for the taken branch indicator
(0x5).
5.7.2 Supervisor Instruction Set
The supervisor instruction set has complete access to the user mode instructions plus the
opcodes shown below. The PST/DDATA specification for these opcodes is shown in
Table 5-23.
The move-to-SR and RTE instructions include an optional PST = 0x3 value, indicating an
entry into user mode. Additionally, if the execution of a RTE instruction returns the
processor to emulator mode, a multiple-cycle status of 0xD is signaled.
Similar to the exception processing mode, the stopped state (PST = 0xE) and the halted
state (PST = 0xF) display this status throughout the entire time the ColdFire processor is in
the given mode.
Instruction
move.w
move.w
wdebug
cpushl
movec
Table 5-23. PST/DDATA Specification for Supervisor-Mode Instructions
stop
halt
rte
Operand Syntax
{Dy,#imm},SR
SR,Dx
<ea>y
Ry,Rc
#imm
PST = 0x1
PST = 0x1,
PST = 0xF
PST = 0x1
PST = 0x1, {PST = 0x3}
PST = 0x1
PST = 0x7, {PST = 0xB, DD = source operand}, {PST = 3}, { PST = 0xB,
DD = source operand},
PST = 0x5, {[PST = 0x9AB], DD = target address}
PST = 0x1,
PST = 0xE
PST = 0x1, {PST = 0xB, DD = source, PST = 0xB, DD = source}
Chapter 5. Debug Support
PST/DDATA
Processor Status, DDATA Definition
5-41