mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 329

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
13.6 Application Examples
This section provides examples for applications.
13.6.1 Introduction
The following section describes the initialization of the PLIC ports and gives three
application examples demonstrating the connection of multiple transceivers or CODECs to
the PLIC module.
Reset
Field NBP
Addr
R/W
14–8
Bits
7–6
5–3
2–0
15
15 14
CMULT
Name
FDIV
NBP
CKI
—
—
Chapter 13. Physical Layer Interface Controller (PLIC)
Figure 13-34. Clock Select Register (PCSR)
Non-bypass mode select for the clock generation module.
0 The clock generation module is bypassed. Gen_FSC and GDCL are connected
1 Selects non-bypassed mode. Gen_FSC and GDCL are synthesized from the
Reserved, should be cleared.
Clock select Input. Selects the source clock for the clock generation block.
00 DCL0
01 FSC0
1x Reserved
FSC divide. Sets the divide ratio between GDCL and Gen_FSC.
000 ÷4
001 ÷8
010 ÷16
011 ÷32
100 ÷64
101 ÷128
110 ÷192
111 ÷256
Clock multiplication ratio. Sets the ratio of the reference clock frequency to the
GDCL frequency.
000 x 2
001 x 4
010 x 8
011 x 16
100 x 23
101 x 64
110 x 128
111 x 256
Table 13-17. PCSR Field Descriptions
to FSC0 and DCL0.
incoming FSC0 or DCL0.
8
7
CKI
0000_0000_0000_0000
6
MBAR + 0x39E
Read/Write
5
Description
FDIV
3
2
Application Examples
CMULT
0
13-33