mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 154

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Background Debug Mode (BDM)
5.5.3.3.10 Write Control Register (
The operand (longword) data is written to the specified control register. The write alters all
32 register bits.
Command/Result Formats:
Command Sequence:
Operand Data:
Result Data:
5.5.3.3.11 Read Debug Module Register (
Read the selected debug module register and return the 32-bit result. The only valid register
selection for the
clears CSR[FOF, TRG, HALT, BKPT]; as well as the trigger status bits (CSR[BSTAT]) if
either a level-2 breakpoint has been triggered or a level-1 breakpoint has been triggered and
no level-2 breakpoint has been enabled.
5-32
Command
WCREG
Result
???
15
RDMREG
"NOT READY"
0x2
0x0
0x0
EXT WORD
MS ADDR
Figure 5-35.
This instruction requires two longword operands. The first selects the
register to which the operand data is to be written; the second
contains the data.
Successful write operations return 0xFFFF. Bus errors on the write
cycle are indicated by the setting of bit 16 in the status message and
by a data pattern of 0x0001.
Figure 5-36.
command is CSR (DRc = 0x00). Note that this read of the CSR
12
11
"NOT READY"
EXT WORD
MS ADDR
WCREG
MCF5272 User’s Manual
WCREG
0x8
0x0
Command/Result Formats
WCREG
Command Sequence
"NOT READY"
"NOT READY"
D[31:16]
MS DATA
8
D[15:0]
LS DATA
)
RDMREG
7
0x8
0x0
Rc
REGISTER
CONTROL
LOCATION
WRITE
MEMORY
)
WRITE
4
3
"NOT READY"
"CMD COMPLETE"
0x0
0x0
BERR
XXX
"NOT READY"
XXX
NEXT CMD
XXX
NEXT CMD
MOTOROLA
0