mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 222

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

DMA Controller Registers
10.3.2 DMA Interrupt Register (DIR)
The DIR, Figure 10-2, contains status bits and their corresponding interrupt enables.
Table 10-3 describes DIR fields.
10-4
Reset
15–13
Field
Addr
Bits
R/W
Bits
4–2
1–0
12
15
SRCS
INVEN
Name
SRCT
Name
—
—
Source addressing type. Used internal to the MCF5272 to qualify the address bits. The value
should be compatible with the CSCRn[TM] value used for external RAM or peripheral device
access.
000 Reserved
001 User data access
010 User code access
011 Reserved
100 Reserved
101 Supervisor data access
110 Supervisor code access
111 Reserved
Source data transfer type. Determines the amount of data the DMA controller fetches and buffers
data from the source address. When there are enough bytes to perform a destination data write of
the size programmed in DSTS, the data is written to the destination address. Thus source
accesses can be longword type and destination addresses can be line burst type. In this case, 4
longword reads are performed followed by an indivisible burst write of 4 longwords.
The most efficient data transfer method is to use longword or line burst transfer types.
Reserved, should be cleared.
Invalid combination interrupt enable.
0 INV interrupt is disabled.
1 INV interrupt is enabled.
13
Table 10-2. DMR Field Descriptions (Continued)
INVEN ASCEN
Figure 10-2. DMA Interrupt Register (DIR)
SRCS
12
00
01
10
11
Table 10-3. DIR Field Descriptions
11
Longword
Byte
Word
16-byte line burst
Data Transfer Type
MCF5272 User’s Manual
—
10
0000_0000_0000_0000
TEEN TCEN
9
MBAR + 0x00E6
R/W
8
Description
Description
1
2
4
16. Valid only for SDRAM.
7
Address Incremented by
—
5
INV
4
ASC
3
—
2
MOTOROLA
TE
1
TC
0