mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 387

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
The two error modes are selected by UMR1n[ERR] as follows:
In either mode, reading the USRn does not affect the FIFO. The FIFO is popped only when
the receive buffer is read. The USRn should be read before reading the receive buffer. If all
24 receiver holding registers are full, a new character is held in the receiver shift register
until space is available. However, if a second new character is received, the character in the
receiver shift register is lost, the FIFO is unaffected, and USRn[OE] is set when the receiver
detects the start bit of the new overrunning character.
Visibility into the status of the FIFO is provided by various bits and interrupts, as shown in
Table 16-17.
To support flow control, the receiver can be programmed to automatically negate and assert
RTS, in which case the receiver automatically negates RTS when a valid start bit is detected
and the FIFO stack is full. The receiver asserts RTS when a FIFO position becomes
available; therefore, overrun errors can be prevented by connecting RTS to the CTS input
of the transmitting device.
• In character mode (UMR1n[ERR] = 0), status is given in the USRn for the character
• In block mode, the USRn shows a logical OR of all characters reaching the top of
at the top of the FIFO.
the FIFO stack since the last
characters reach the top of the FIFO stack. Block mode offers a data-reception speed
advantage where the software overhead of error-checking each character cannot be
tolerated. However, errors are not detected until the check is performed at the end of
an entire message—the faulting character in the block is not identified.
USR[FFULL] = 1
USR[RxRDY] = 1
USR[RxFIFO] = 1
USR[RxFTO] = 1
URF[RXS]
URF[RXB]
Status Bit
The receiver can still read characters in the FIFO stack if the
receiver is disabled. If the receiver is reset, the FIFO stack, RTS
control, all receiver status bits, and interrupt requests are reset.
No more characters are received until the receiver is reenabled.
All FIFO positions contain data
At least one character is available to be read by the CPU.
The programmed level of fullness (UTF[RXS]) has been reached.
The receiver FIFO holds unread data, and the FIFO status has not
changed in at least 64 receiver clocks.
Indicates the level of fullness of the receiver FIFO
Indicates the number of characters, 0–24, in the receiver FIFO.
Table 16-17. Receiver FIFO Status Bits
Chapter 16. UART Modules
RESET ERROR STATUS
Indicated Condition
NOTE:
command. Status is updated as
Interrupt
Yes
Yes
Yes
Yes
Operation
16-27